metronome/hardware/LAYOUT_REFERENCES.md

PM_K-1 — Per-Stage Layout References

LAYOUT.md has our rules (general principles for this board). This file points at the manufacturers' own reference layouts, EVMs, and layout app-notes for each stage — so whoever routes the board can follow proven examples instead of working from first principles. Two of these are essentially our exact circuit.

⭐ = a reference design / EVM that closely matches what we built (highest value).

Power — switching supply (TPS65131) — the most layout-critical stage

• ⭐ TPS65131EVM-839 (the eval board) + its User's Guide SLVUAW7. https://www.ti.com/tool/TPS65131EVM-839 · https://www.ti.com/lit/ug/slvuaw7/slvuaw7.pdf Takeaway: 4-layer, all parts top side; switching nodes isolated from the feedback network, careful high-frequency current routing, separate analog & power grounds, feedback components small/closely-spaced. TI explicitly says "follow the EVM layout."
• Datasheet layout section: TPS65131 (SLVS493E) — already in datasheets/.

Power — clean ±15 V LDOs (TPS7A4901 / TPS7A3001)

• ⭐ TPS7A30-49EVM-567 — a dual EVM with −15 V and +15 V outputs = our exact rails. https://www.ti.com/tool/TPS7A30-49EVM-567 (search TI for the user's guide) Takeaway: the reference layout for the exact LDO pair we use.
• Datasheet rule (TPS7A49/TPS7A30): separate IN and OUT ground planes joined only at the GND pin; keep the NR/SS cap and feedback divider tight; ~2 dB PSRR from good grounding. https://www.ti.com/lit/ds/symlink/tps7a49.pdf · https://www.ti.com/lit/ds/symlink/tps7a30.pdf E2E thread on layout + resistor selection: https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/238266/

MCU (RP2350)

• ⭐ Official RP2350 "Minimal" KiCad design files (schematic + symbols + footprints + the minimal layout): https://datasheets.raspberrypi.com/rp2350/Minimal-KiCAD.zip Takeaway: fork this — it's the authoritative layout for the core SMPS inductor loop, decoupling, crystal, QSPI, and USB. (Also a clean source for the RP2350 + QFN footprints.)
• Hardware design with RP2350 (RP-008280) — in datasheets/ (decoupling-per-pin, crystal, QSPI-short, USB 27 Ω series, VREG_AVDD filter).
• Third-party open board: Olimex RP2350-PICO2-BB48 (full open KiCad). https://www.olimex.com/Products/RaspberryPi/PICO/RP2350-PICO2-BB48/open-source-hardware

DAC (PCM5102A)

• Datasheet layout section: PCM5102A (SLAS859C) — in datasheets/.
• Widely-cloned reference: the GY-PCM5102 module + community layouts. diyAudio: https://www.diyaudio.com/community/threads/dac-design-based-on-pcm5102a.410231/ · KiCad forum: https://forum.kicad.info/t/how-do-i-design-a-pcm5102a-dac/56441 Takeaway: one solid ground plane (well-segmented), decoupling (10 nF + 100 nF) within ~5 mm of VDD, full copper pour under the IC, ground-via grid, short I²S traces.

Balanced audio (THAT1240 receiver / THAT1646 driver)

• THAT product pages (have app guidance + reference circuits): https://thatcorp.com/that-1606-1646-balanced-line-driver-ics/ · audio design resources: https://thatcorp.com/Audio_Design_Resources.php
• Community reference layouts: theslowdiyer THAT1646 board https://theslowdiyer.wordpress.com/tag/that1646/ · Elektor "Balanced Audio Line Driver" https://www.elektormagazine.com/labs/balanced-audio-line-driver Takeaway: 22 Ω + decoupling caps right at the ±15 V pins; DC-block "link" caps; RFI filter (series R/ferrite + small cap) at the connector; keep input and output apart; route HOT/COLD as a tight pair.

Op-amps (OPA1641 / OPA1612 — filter, summer, DI buffer)

• TI SBOA092B — Handbook of Operational Amplifier Applications: https://www.ti.com/lit/an/sboa092b/sboa092b.pdf
• TI SLOA046 / SLOA102 — amplifier layout app-notes: https://www.ti.com/lit/an/sloa046/sloa046.pdf
• TI Precision Hub "The basics: how to layout a PCB for an op amp": https://e2e.ti.com/blogs_/archives/b/precisionhub/posts/the-basics-how-to-layout-a-pcb-for-an-op-amp Takeaway: decoupling < 0.1 in from the supply pins; feedback resistor right at the inverting input (minimal loop area / parasitic C); short input traces; ground plane under; keep input and output apart for channel isolation.

RTC (RV-8803-C7)

• RV-8803-C7 Application Manual (rev 1.6) — §"Dimensions and Solder Pad Layout" + "Recommended Thermal Relief" (≈ p65–66): https://www.microcrystal.com/fileadmin/Media/Products/RTC/App.Manual/RV-8803-C7_App-Manual.pdf (EM Microelectronic mirror: https://www.emmicroelectronic.com/sites/default/files/products/datasheets/rv-8803-c7-mn01.pdf)
• Ready footprint (verify against ours): SnapEDA RV-8803-C7-TA-QC. Takeaway: confirms the SON-8 pad land pattern we built + thermal relief.

USB (USB-C receptacle + USBLC6-2SC6 ESD)

• USB-C routing guides: PCBWay https://www.pcbway.com/blog/PCB_Design_Layout/USB_Type_C_PCB_Design_Guidelines_Layout_and_Routing_Best_Practices_55bc0c39.html · Cadence https://resources.pcb.cadence.com/blog/2024-impedance-matching-for-usb-interfaces-in-pcbs · Altium (2-layer USB) https://resources.altium.com/p/routing-requirements-usb-20-2-layer-pcb Takeaway: D± = 90 Ω ±10 % differential pair, skew < 15 ps (~100 mil), ground on both sides (gap ≤ 3× trace width). Place the USBLC6-2 within ~100–200 mil of the connector, before any other component, no vias between connector and diode (vias slow the clamp).

Class-D speaker amp (PAM8302A, DNP)

• TI Class-D layout app-note (applies to filterless BTL output): SLAA896 / SLAA902 https://www.ti.com/lit/an/slaa896/slaa896.pdf Takeaway: keep the BTL output traces short and symmetric; add the EMI ferrite/cap near the output if cabling is long; the switching output is noisy — keep it away from the analog input.

Relay (TQ2SA), ULN2003, LM393

• Straightforward digital/contact layout: relay contact traces wide enough for the switched current; ULN2003 flyback (COM to the coil supply) close; LM393 standard comparator layout. Panasonic TQ-SMD datasheet (in datasheets/) has the recommended mounting pad.

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The three to prioritize (the hard parts)

1. TPS65131EVM-839 / SLVUAW7 — copy the switcher layout almost verbatim.
2. TPS7A30-49EVM-567 — it's literally the ±15 V dual-LDO layout we need.
3. RP2350 Minimal-KiCAD.zip — fork the MCU/USB/crystal/QSPI layout.

Hand these (plus LAYOUT.md) to whoever routes the board; they cover every stage where layout — not schematic — determines whether it works.

Saved locally (in hardware/datasheets/, git-ignored)

The three priority references are downloaded for offline use:

• TPS65131EVM_SLVUAW7.pdf — switcher EVM, includes the full 4-layer PCB plots (Top / Inner 1 / Inner 2 / Bottom) + BOM (which matches our TPS65131RGER / 4.7 µH / MBRM120). Copy this layout for the switcher block.
• TPS7A30-49EVM_SLVU405.pdf — the ±15 V dual-LDO EVM (schematic + layout + thermal + BOM).
• RP2350-Minimal-KiCAD.zip — official RP2350 reference. Nested: unzip it, then extract RP-006440-...RP2350A Minimal Board Kicad archive.zip (RP2350A / QFN-60 = our part) for the schematic + PCB + footprints; the RP-006442 archive is the QFN-80 (RP2350B) variant.