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Me Here 617bb5a8b2 PM_K-1 hardware: integrate audio chain into one netlist (dedup shared parts) 
circuits/audio_chain.py wires stages 1/1b/2/3/4 with shared nets and deduplicated
parts: ONE OPA1612 (U4) does both the Stage-2 filter (A) and Stage-3 summer (B);
ONE ULN2003 (U6) drives all three relays (K1 select, K2 mute, K3 ground-lift).
54 components, ERC 0 errors, netlist 0 errors. Per-stage files remain as the
documented, individually-simulated building blocks.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
2026-05-30 20:41:39 -05:00
..
.gitignore PM_K-1 hardware: Stage 1 input receiver as SKiDL (code-defined schematic) 2026-05-30 19:43:07 -05:00
audio_chain.erc PM_K-1 hardware: integrate audio chain into one netlist (dedup shared parts) 2026-05-30 20:41:39 -05:00
audio_chain.log PM_K-1 hardware: integrate audio chain into one netlist (dedup shared parts) 2026-05-30 20:41:39 -05:00
audio_chain_sklib.py PM_K-1 hardware: integrate audio chain into one netlist (dedup shared parts) 2026-05-30 20:41:39 -05:00
pm_k1_core.kicad_pro PM_K-1 hardware: core-board design-of-record + KiCad scaffold 2026-05-30 11:42:45 -05:00
pm_k1_core.kicad_sch PM_K-1 hardware: core-board design-of-record + KiCad scaffold 2026-05-30 11:42:45 -05:00
skidl.erc PM_K-1 hardware: Stage 1 input receiver as SKiDL (code-defined schematic) 2026-05-30 19:43:07 -05:00
skidl.log PM_K-1 hardware: Stage 1 input receiver as SKiDL (code-defined schematic) 2026-05-30 19:43:07 -05:00
skidl_REPL.erc PM_K-1 hardware: Stage 1 audio (input receiver) sims + container libs 2026-05-30 19:27:25 -05:00
skidl_REPL.log PM_K-1 hardware: Stage 1 audio (input receiver) sims + container libs 2026-05-30 19:27:25 -05:00
stage1_input.erc PM_K-1 hardware: Stage 1 input receiver as SKiDL (code-defined schematic) 2026-05-30 19:43:07 -05:00
stage1_input.log PM_K-1 hardware: verify THAT1240 against datasheet; fix pinout + part numbers 2026-05-30 19:48:41 -05:00
stage1_input_sklib.py PM_K-1 hardware: verify THAT1240 against datasheet; fix pinout + part numbers 2026-05-30 19:48:41 -05:00
stage1b_select.erc PM_K-1 hardware: Stage 1b -- Hi-Z instrument DI buffer + line/inst select relay 2026-05-30 19:56:55 -05:00
stage1b_select.log PM_K-1 hardware: Stage 1b -- Hi-Z instrument DI buffer + line/inst select relay 2026-05-30 19:56:55 -05:00
stage1b_select_sklib.py PM_K-1 hardware: Stage 1b -- Hi-Z instrument DI buffer + line/inst select relay 2026-05-30 19:56:55 -05:00
stage2_dac.erc PM_K-1 hardware: resolve TQ2SA relay pinout; Stage 2 DAC + reconstruction filter 2026-05-30 20:06:26 -05:00
stage2_dac.log PM_K-1 hardware: resolve TQ2SA relay pinout; Stage 2 DAC + reconstruction filter 2026-05-30 20:06:26 -05:00
stage2_dac_sklib.py PM_K-1 hardware: resolve TQ2SA relay pinout; Stage 2 DAC + reconstruction filter 2026-05-30 20:06:26 -05:00
stage3_sum.erc PM_K-1 hardware: Stage 3 -- summing node (selected input + click) 2026-05-30 20:15:17 -05:00
stage3_sum.log PM_K-1 hardware: Stage 3 -- summing node (selected input + click) 2026-05-30 20:15:17 -05:00
stage3_sum_sklib.py PM_K-1 hardware: Stage 3 -- summing node (selected input + click) 2026-05-30 20:15:17 -05:00
stage4_driver.erc PM_K-1 hardware: Stage 4 -- balanced output driver (completes the audio chain) 2026-05-30 20:27:04 -05:00
stage4_driver.log PM_K-1 hardware: Stage 4 -- balanced output driver (completes the audio chain) 2026-05-30 20:27:04 -05:00
stage4_driver_sklib.py PM_K-1 hardware: Stage 4 -- balanced output driver (completes the audio chain) 2026-05-30 20:27:04 -05:00