eef535f9ef
ST7796S datasheet §10.8: panel rescans GRAM at 60Hz; tear-free writes require feeding the TE output back to the MCU and writing during vblank. EP-0172 prototype wires no TE, so large updates tear (small writes hide it — why MP/CP look clean). Add TE (e.g. GP4) + optional MISO to the face interconnect for the production board. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
221 lines
13 KiB
Markdown
221 lines
13 KiB
Markdown
# PM_K-1 Core Board ("brain") — design-of-record
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VARASYS PolyMeter · heirloom pro-audio · modular brain/face architecture
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Status: **design-of-record / pre-layout.** Component selection complete; PCB routing is the
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remaining interactive step (see [Open items](#open-items)).
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---
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## 1. Philosophy
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This is meant to be a device people hand down to their great-grandkids. The core board carries
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**all the active electronics** and is specced to pro/audiophile tier with longevity and
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serviceability as first-class goals. We do **not** value-engineer the audio path.
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The user selects the face/enclosure/connector components; this document specs only the **core**.
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## 2. Architecture — modular brain/face
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- **Core ("brain"):** RP2350 + power + RTC + the full pro-audio analog chain + control logic.
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One core design is reused across every form factor.
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- **Face ("form factor"):** display, touch, joystick, buttons, LED, speaker, the physical
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audio/MIDI connectors, panel switches, enclosure. **The core never decides connector type.**
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- **Two interconnects, deliberately separate** (§7):
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1. a **digital ribbon** whose pinout mirrors the Raspberry Pi Pico, so a stock Pico/Pico 2 on a
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test adapter can drive any face board for bring-up;
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2. an **analog interconnect** (+ a small MIDI interconnect) kept physically away from the fast
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digital ribbon, because a balanced audio signal must never run parallel to the 24 MHz display SPI.
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## 3. Block diagram
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```
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USB-C 5V ─┬─► 3V3 LDO ──────────────────────► RP2350 (core reg + ext L) + W25Q128 16MB + RV-8803 RTC(+CR2032)
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│ │ I²S + low-jitter MCLK
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└─► TPS65131 ±18V ─► TPS7A49/30 LDO ─► clean ±15V ▼
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PCM5102A DAC ──► [summing: click + input]
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│
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bal IN ─[ESD/DC-block/clamp/series-R]─► [LINE/INST relay] ─┬─ THAT1240 receiver ──┘
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(analog interconnect) └─ OPA1641 Hi-Z DI buffer (+gain)
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│
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THAT1646 balanced driver ─[47Ω build-out]─► [MUTE relay]─► bal OUT
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shield ─[panel SW]─[GND-LIFT relay]─ gnd
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sig/clip peak detect ─► LM393 ─► RP2350 GPIO (UI) + LED lines (interconnect)
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RP2350 UART ─► [DNP: H11L1 opto IN + 74LVC14 buffer OUT] ─► MIDI interconnect (USB-MIDI = default)
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```
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## 4. Functional blocks
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### 4.1 MCU + digital
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- **RP2350A** (QFN-60, 30 GPIO). Chosen over RP2040 as the newest in-house part: dual M33+RISC-V,
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520 KB RAM, secure boot, longest production runway. Firmware runs unchanged.
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- **Erratum E9:** high-impedance inputs can latch — every input we read (face switches, buttons)
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gets an **external pulldown**, never relies on the internal pad alone.
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- Core supply via the RP2350 on-chip switched-mode regulator (external inductor); 3V3 IO from an
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external LDO (AP2112K-3.3 / TLV75533).
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- **Flash:** Winbond **W25Q128JV** (16 MB) — genuine part; the CircuitPython appliance bundles the
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editor + tracks on a USB drive. Firmware does wear-leveling for `history.json`.
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- **Crystal:** 12 MHz ±30 ppm.
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- **Debug/service:** SWD 2×5 Cortex-Debug header + labeled test points (rails, I²S, audio nodes).
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### 4.2 Click source (DAC)
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- **TI/Burr-Brown PCM5102A** I²S DAC — reliability-first, widely stocked for future repair.
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- Fed by a **dedicated low-jitter audio oscillator** (22.5792/24.576 MHz MEMS XO), **not** an MCLK
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jittered out of the RP2350 PIO — jitter is audible as a raised noise floor.
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### 4.3 Analog audio chain (the heart)
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- **Input (balanced, switchable line/instrument):**
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- **Line mode:** THAT1240 laser-trimmed balanced receiver (~high CMRR, no hand-matched resistors).
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- **Instrument mode:** OPA1641 JFET Hi-Z buffer (≥1 MΩ) + ~+10–15 dB gain (active DI).
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- Selected by a **gold-contact signal relay** on the core (1 GPIO; touchscreen toggle, optional
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face panel switch on a separate GPIO input).
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- **Protection (non-negotiable):** series DC-blocking film cap (blocks +48 V phantom — the real
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input-killer), clamp diodes/TVS to the rails, series current-limit resistor. A wrong-mode plug
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then only *sounds* wrong; nothing is damaged.
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- **Mix:** digital/firmware (touchscreen). Analog stage at unity; click level set via the DAC.
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- **Output driver:** THAT1646 balanced line driver, **47 Ω build-out per leg** for
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cable-capacitance stability and short-circuit tolerance (§5.1).
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- **No electrolytics in the signal path** — film coupling caps (WIMA). 0.1 % thin-film resistors.
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### 4.4 Output protection / conditioning
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- **Power-up/down mute relay** — fail-safe, **de-energized = muted** (shorts hot+cold to gnd). A
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hardware rail supervisor + RC turn-on delay un-mutes only after ±15 V settles; on power loss the
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coil drops and mutes *faster than the rails can thump*. **Not MCU-dependent.** The MCU can *also*
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assert mute (for clean line/inst flips and DAC reconfig).
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- **Ground-lift** — both a **face panel switch** and a **core GPIO relay**, wired in **series** in
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the shield-ground path: bonded only when both closed, either opening lifts it. **Soft lift =
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100 Ω ∥ 10 nF** (not a hard open) so RF/safety keeps a path.
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### 4.5 RTC
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- **Micro Crystal RV-8803** (integrated 32.768 kHz crystal → no second crystal near the RP2350's
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own) + **CR2032 in a socketed holder**. Shares the touch I²C bus (no extra GPIO). Drift is
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irrelevant for a practice-log timestamp; reliability and zero-fuss layout win.
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### 4.6 MIDI (default USB, hardware optional)
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- **USB-MIDI is the default** and already in firmware — IN/OUT/THRU are software routing to a
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computer/tablet host. Zero extra parts.
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- **Dedicated DIN/TRS MIDI is a DNP populate-option:** the RP2350 UART lines route to the MIDI
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interconnect with **H11L1 opto IN + 74LVC14 buffered OUT/THRU footprints left unpopulated**.
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A "stage" face can populate them for laptop-free hardware sync. (USB-MIDI can't peer-to-peer with
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standalone DIN gear — the device is a USB *peripheral*, not a host — which is why the hardware
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option stays available.) Analog pulse/clock sync: **not included** (MIDI only).
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### 4.7 Monitor speaker
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- **DNP-optional** class-D amp (PAM8302) footprint on the core; speaker +/- routed on the analog
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interconnect. Populated only for form factors that want a built-in monitor.
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## 5. The five remaining pro details (decided)
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### 5.1 Output impedance & level calibration
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- THAT1646 source impedance is near-zero; **47 Ω build-out resistors** per leg give stable driving
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into long/capacitive cables and survive a shorted output.
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- **Level calibration:** a 25-turn precision trimmer (Bourns 3296W) in the driver gain network,
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factory-set so DAC full-scale → **+4 dBu nominal**, leaving ~**+24 dBu** peak headroom on ±15 V.
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Set-and-forget on the core; not a face control.
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### 5.2 Signal / clip indication
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- A peak detector (Schottky + hold cap) on the input (signal-present, ~−40 dBu) and on the
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driver-input/summing node (clip, within ~3 dB of rail) feeds an **LM393** dual comparator.
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- Comparator outputs go to **RP2350 GPIOs** (clip/signal shown on the touchscreen) **and** are
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mirrored to **SIG/CLIP LED drive lines on the digital interconnect** so a face can fit discrete LEDs.
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### 5.3 ESD / EMI hardening
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- **USB-C:** USBLC6-2SC6 (or TPD4E05U06) ESD array on D±/CC/VBUS; common-mode choke on the data
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pair; shell bonded to chassis via RC; ferrite + TVS + bulk on VBUS.
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- **Interconnects:** ~33 Ω series on fast SPI lines for edge-rate control; ESD clamp arrays on any
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line reaching a user-touchable cable; interleaved ground pins; ferrite beads where 3V3/5V cross
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into the analog domain.
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- **Board:** full ground planes + stitching vias; the boost/inverter switcher lives in a guarded
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corner away from the analog section; analog/digital grounds meet at a single **star point**.
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- **Heirloom option:** conformal coating for humidity/longevity (build-time choice).
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### 5.4 Chassis / strain-relief (core-side)
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- 4× **M3 mounting holes** with keep-outs; a dedicated chassis-ground pad/pin.
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- **Through-hole-anchored USB-C** jack (SMD-only tabs shear off with cable wiggle — unacceptable for
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a 50-year device).
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- **Shrouded, keyed, latching** interconnect headers (can't insert backward or vibrate loose).
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- Panel strain-relief and connector mounting live on the face/enclosure.
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### 5.5 Interconnect pinout — see §7.
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## 6. Power tree
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| Rail | Source | Part | Notes |
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|---|---|---|---|
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| +5 V | USB-C VBUS | — | ferrite + TVS + bulk |
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| +3V3 (IO) | LDO from 5 V | AP2112K-3.3 / TLV75533 | digital domain |
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| +1.1 V core | RP2350 internal SMPS | (external inductor) | per RP2350 ref |
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| ±18 V (raw) | dual boost/inverter from 5 V | **TPS65131** | switcher, guarded corner |
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| **±15 V (clean)** | ultra-low-noise LDO | **TPS7A4901 (+) / TPS7A3001 (−)** | feeds all audio op-amps |
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## 7. Interconnect pinouts
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### 7.1 Digital ribbon — 2×13 (26-pin) IDC, Pico-pinout-compatible
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Grounds interleaved around SPI. A Pico/Pico 2 test adapter maps these to the listed GP.
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| Pin | Signal | GP | | Pin | Signal | GP |
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|----|--------|----|--|----|--------|----|
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| 1 | +5V | — | | 2 | GND | — |
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| 3 | +3V3 | — | | 4 | GND | — |
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| 5 | SPI_SCK | GP2 | | 6 | GND | — |
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| 7 | SPI_MOSI | GP3 | | 8 | LCD_CS | GP5 |
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| 9 | LCD_DC | GP6 | | 10 | LCD_RST | GP7 |
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| 11 | GND | — | | 12 | I2C_SDA | GP8 |
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| 13 | I2C_SCL | GP9 | | 14 | GND | — |
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| 15 | JOY_X (ADC0) | GP26 | | 16 | JOY_Y (ADC1) | GP27 |
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| 17 | BTN_A | GP15 | | 18 | BTN_B | GP14 |
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| 19 | WS2812 | GP12 | | 20 | GND | — |
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| 21 | GNDLIFT_SW (in) | GP21 | | 22 | LINEINST_SW (in) | GP22 |
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| 23 | SIG_LED | GP19 | | 24 | CLIP_LED | GP20 |
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| 25 | GND | — | | 26 | GND | — |
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*I²S (BCK/LRCK/DOUT), the relays (line/inst route GP16, mute GP18, gnd-lift GP17), and MCLK stay
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on-core — they are not on the ribbon. A Pico test brain drives the digital/face I/O above but
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**cannot** drive the analog chain (DAC/op-amps are core-only).*
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> **Display TE line — route it on the production face.** The table above mirrors the EP-0172
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> prototype, which wires only SCK/MOSI/CS/DC/RST and **no TE (tearing-effect) output**. Per the
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> ST7796S datasheet §10.8, the panel rescans its frame memory to the glass at 60 Hz and the *only*
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> sanctioned way to avoid tearing is to feed the **TE output back to the MCU** and write during
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> vblank (`tvdh`). Without it, large updates tear and only small sub-region writes hide it (this is
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> why MicroPython/CircuitPython, which draw glyph-by-glyph, look clean and the Rust full-frame blits
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> don't). **Add the LCD `TE` pin to a spare GPIO (e.g. GP4)** on the face interconnect — and
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> optionally LCD `MISO`/`SDO` for `GSCAN`(45h)/status reads. Then firmware can do
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> `TEON`(35h)+vblank-synced writes and be fully tear-free even on full repaints.
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### 7.2 Analog audio interconnect — 2×5 (10-pin), twisted/shielded, away from digital
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| Pin | Signal | | Pin | Signal |
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|----|--------|--|----|--------|
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| 1 | AOUT_HOT | | 2 | AGND |
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| 3 | AOUT_COLD | | 4 | CHASSIS/SHIELD (face side of ground-lift) |
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| 5 | AIN_HOT | | 6 | AGND |
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| 7 | AIN_COLD | | 8 | SPK+ (DNP) |
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| 9 | AGND | | 10 | SPK− (DNP) |
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### 7.3 MIDI interconnect — 1×6, only if DNP MIDI populated
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| Pin | Signal |
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|----|--------|
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| 1 | MIDI_OUT_A (TRS-A tip/ring leg) |
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| 2 | MIDI_OUT_B |
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| 3 | MIDI_IN_A (to opto) |
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| 4 | MIDI_IN_B |
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| 5 | +5V (OUT drive) |
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| 6 | GND / shield |
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## 8. BOM
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Full part list with manufacturer numbers and rough costs in **`hardware/BOM.csv`**. Headline parts:
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RP2350A · W25Q128JV · PCM5102A · THAT1240 + THAT1646 · OPA1641 · OPA1612 · TPS65131 + TPS7A4901/3001 ·
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RV-8803 · USBLC6-2SC6 · 3× Panasonic TQ2SA gold-contact relays · H11L1 (DNP).
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## 9. Manufacturing
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- **PCB:** ENIG (gold) finish — non-negotiable for decades of reliable contacts/solderability.
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- **Assembly:** JLCPCB/PCBWay PCBA, ~5-board prototype minimum; ~$80–200 first run. Core parts cost
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~$25–40/board one-off (pro op-amps + relays dominate), trending toward ~$15–20 at qty 100.
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- Most expensive items are the THAT audio ICs and the relays — that's where "heirloom" lives.
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## 10. Open items
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- **PCB layout/routing is the interactive next step** — placement, controlled-impedance USB pair,
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star ground, switcher isolation, copper pours, DRC. The KiCad project under `hardware/kicad/`
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is a documented schematic canvas + design-of-record; symbol placement and wiring happen in
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Eeschema. `kicad-cli` is used here for ERC and PDF export verification.
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- Confirm the exact 3.5" ST7796/GT911 panel connector (FPC vs header) before finalizing the face.
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- Decide MIDI connector (TRS-MIDI Type-A vs DIN-5) per form factor — face decision.
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