Me Here 39fe087b2c PM_K-1 hardware: per-block schematic SVGs (netlistsvg) so the design is viewable ...

Added Node.js + netlistsvg to the EDA container; make_svg.py renders a SKiDL block to a
schematic SVG. Generated hardware/eda/schematics/*.svg for 12 blocks (audio stages 1-4 +
integrated, power tree, RP2350 core, RTC, MIDI, indicator, speaker) -- open in a browser.
Auto-routed (functional, not pretty); per-block so they're readable. interconnect omitted
(netlistsvg layout engine errors on the 24-pin USB-C + headers; its mapping is in DESIGN.md
s7). Intermediates (.json/_skin.svg) git-ignored.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>

2026-05-31 16:42:04 -05:00

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