History

Me Here 39fe087b2c PM_K-1 hardware: per-block schematic SVGs (netlistsvg) so the design is viewable Added Node.js + netlistsvg to the EDA container; make_svg.py renders a SKiDL block to a schematic SVG. Generated hardware/eda/schematics/*.svg for 12 blocks (audio stages 1-4 + integrated, power tree, RP2350 core, RTC, MIDI, indicator, speaker) -- open in a browser. Auto-routed (functional, not pretty); per-block so they're readable. interconnect omitted (netlistsvg layout engine errors on the 24-pin USB-C + headers; its mapping is in DESIGN.md s7). Intermediates (.json/_skin.svg) git-ignored. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>		2026-05-31 16:42:04 -05:00
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.gitignore	PM_K-1 hardware: per-block schematic SVGs (netlistsvg) so the design is viewable	2026-05-31 16:42:04 -05:00
audio_chain.svg	PM_K-1 hardware: per-block schematic SVGs (netlistsvg) so the design is viewable	2026-05-31 16:42:04 -05:00
indicator.svg	PM_K-1 hardware: per-block schematic SVGs (netlistsvg) so the design is viewable	2026-05-31 16:42:04 -05:00
mcu_core.svg	PM_K-1 hardware: per-block schematic SVGs (netlistsvg) so the design is viewable	2026-05-31 16:42:04 -05:00
midi.svg	PM_K-1 hardware: per-block schematic SVGs (netlistsvg) so the design is viewable	2026-05-31 16:42:04 -05:00
power_tree.svg	PM_K-1 hardware: per-block schematic SVGs (netlistsvg) so the design is viewable	2026-05-31 16:42:04 -05:00
README.md	PM_K-1 hardware: per-block schematic SVGs (netlistsvg) so the design is viewable	2026-05-31 16:42:04 -05:00
rtc.svg	PM_K-1 hardware: per-block schematic SVGs (netlistsvg) so the design is viewable	2026-05-31 16:42:04 -05:00
speaker.svg	PM_K-1 hardware: per-block schematic SVGs (netlistsvg) so the design is viewable	2026-05-31 16:42:04 -05:00
stage1_input.svg	PM_K-1 hardware: per-block schematic SVGs (netlistsvg) so the design is viewable	2026-05-31 16:42:04 -05:00
stage1b_select.svg	PM_K-1 hardware: per-block schematic SVGs (netlistsvg) so the design is viewable	2026-05-31 16:42:04 -05:00
stage2_dac.svg	PM_K-1 hardware: per-block schematic SVGs (netlistsvg) so the design is viewable	2026-05-31 16:42:04 -05:00
stage3_sum.svg	PM_K-1 hardware: per-block schematic SVGs (netlistsvg) so the design is viewable	2026-05-31 16:42:04 -05:00
stage4_driver.svg	PM_K-1 hardware: per-block schematic SVGs (netlistsvg) so the design is viewable	2026-05-31 16:42:04 -05:00

README.md

Schematic views (auto-generated)

Per-block schematic images of the PM_K-1 core board, rendered from the SKiDL circuits with netlistsvg. Open any .svg in a web browser.

What these are: functional, auto-routed schematics (boxes + wires) for tracing connections — not hand-arranged, pretty EE drawings. Each file is one block, so it's readable; the full 167-part board would be an unreadable hairball.

File	Block
`stage1_input.svg`	balanced line receiver + protection
`stage1b_select.svg`	Hi-Z instrument DI buffer + select relay
`stage2_dac.svg`	PCM5102A DAC + reconstruction filter
`stage3_sum.svg`	summing node
`stage4_driver.svg`	balanced output driver + mute + ground-lift
`audio_chain.svg`	the five audio stages integrated (busier)
`power_tree.svg`	±18 V switcher → ±15 V LDOs + 3V3
`mcu_core.svg`	RP2350 + flash + crystal + USB + boot/SWD
`rtc.svg`	RV-8803 RTC + coin-cell backup
`midi.svg`	DNP opto IN + buffered OUT/THRU
`indicator.svg`	SIG/CLIP detector
`speaker.svg`	monitor speaker amp

interconnect is intentionally absent — netlistsvg's layout engine errors on the 24-pin USB-C + many headers. Its connections are pure pin-to-net mapping, fully tabulated in hardware/DESIGN.md §7 and circuits/interconnect.py.

Regenerate (inside the container): for each block, ./run.sh python3 ../eda/make_svg.py circuits/<block>.py schematics/<block> then netlistsvg schematics/<block>.json -o schematics/<block>.svg --skin schematics/<block>_skin.svg.

For the authoritative, hand-written design intent see the circuits/*.py files and hardware/DESIGN.md block diagrams; for the connection list see hardware/kicad/board.net.