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Me Here edb736c1d3 PM_K-1 hardware: RP2350 core (MCU + flash + crystal + USB + boot/reset + SWD) 
circuits/mcu_core.py using the authoritative KiCad MCU_RaspberryPi:RP2350A symbol.
Minimal design per RP "Hardware design with RP2350" (RP-008280):
- Core SMPS: VREG_VIN<-3V3, VREG_LX->3.3uH->DVDD, VREG_FB senses DVDD; VREG_AVDD via
  33ohm+4.7uF RC filter; ADC_AVDD filtered; 100nF per power pin.
- 12MHz crystal, MCLK-LESS (RP2350 makes I2S BCK/LRCK/DIN; PCM5102A uses its internal
  PLL) -- no audio oscillator, no MCLK net. Cheaper/simpler/robust; inaudible difference
  for a metronome (decided with the user).
- W25Q128JVS QSPI flash (Fig-8 pinout); BOOTSEL = QSPI_SS via 1k + button; RUN 10k
  pull-up + reset button; SWD header; USB D+/D- via 27ohm series.
- Full GPIO map assigned (DESIGN.md s7.1 + audio control: SPI/I2C/ADC/buttons/LED +
  I2S + relay-enable/mute/gnd-lift + DAC_XSMT).
ERC 0 errors; netlist 0 errors. CONFIRM at layout: crystal load caps, QFN-60 footprint,
and the USB-C connector + USBLC6-2 ESD + CC resistors (USB sub-block; D+/D- exit on 27R).

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
2026-05-30 21:56:12 -05:00
..
.gitignore PM_K-1 hardware: Stage 1 input receiver as SKiDL (code-defined schematic) 2026-05-30 19:43:07 -05:00
audio_chain.erc PM_K-1 hardware: integrate audio chain into one netlist (dedup shared parts) 2026-05-30 20:41:39 -05:00
audio_chain.log PM_K-1 hardware: integrate audio chain into one netlist (dedup shared parts) 2026-05-30 20:41:39 -05:00
audio_chain_sklib.py PM_K-1 hardware: integrate audio chain into one netlist (dedup shared parts) 2026-05-30 20:41:39 -05:00
mcu_core.erc PM_K-1 hardware: RP2350 core (MCU + flash + crystal + USB + boot/reset + SWD) 2026-05-30 21:56:12 -05:00
mcu_core.log PM_K-1 hardware: RP2350 core (MCU + flash + crystal + USB + boot/reset + SWD) 2026-05-30 21:56:12 -05:00
mcu_core_sklib.py PM_K-1 hardware: RP2350 core (MCU + flash + crystal + USB + boot/reset + SWD) 2026-05-30 21:56:12 -05:00
pm_k1_core.kicad_pro PM_K-1 hardware: core-board design-of-record + KiCad scaffold 2026-05-30 11:42:45 -05:00
pm_k1_core.kicad_sch PM_K-1 hardware: core-board design-of-record + KiCad scaffold 2026-05-30 11:42:45 -05:00
power_tree.erc PM_K-1 hardware: power tree (USB 5V -> +/-18V switcher -> clean +/-15V LDOs + 3V3) 2026-05-30 20:53:44 -05:00
power_tree.log PM_K-1 hardware: power tree (USB 5V -> +/-18V switcher -> clean +/-15V LDOs + 3V3) 2026-05-30 20:53:44 -05:00
power_tree_sklib.py PM_K-1 hardware: power tree (USB 5V -> +/-18V switcher -> clean +/-15V LDOs + 3V3) 2026-05-30 20:53:44 -05:00
skidl.erc PM_K-1 hardware: Stage 1 input receiver as SKiDL (code-defined schematic) 2026-05-30 19:43:07 -05:00
skidl.log PM_K-1 hardware: Stage 1 input receiver as SKiDL (code-defined schematic) 2026-05-30 19:43:07 -05:00
skidl_REPL.erc PM_K-1 hardware: Stage 1 audio (input receiver) sims + container libs 2026-05-30 19:27:25 -05:00
skidl_REPL.log PM_K-1 hardware: Stage 1 audio (input receiver) sims + container libs 2026-05-30 19:27:25 -05:00
stage1_input.erc PM_K-1 hardware: Stage 1 input receiver as SKiDL (code-defined schematic) 2026-05-30 19:43:07 -05:00
stage1_input.log PM_K-1 hardware: verify THAT1240 against datasheet; fix pinout + part numbers 2026-05-30 19:48:41 -05:00
stage1_input_sklib.py PM_K-1 hardware: verify THAT1240 against datasheet; fix pinout + part numbers 2026-05-30 19:48:41 -05:00
stage1b_select.erc PM_K-1 hardware: Stage 1b -- Hi-Z instrument DI buffer + line/inst select relay 2026-05-30 19:56:55 -05:00
stage1b_select.log PM_K-1 hardware: Stage 1b -- Hi-Z instrument DI buffer + line/inst select relay 2026-05-30 19:56:55 -05:00
stage1b_select_sklib.py PM_K-1 hardware: Stage 1b -- Hi-Z instrument DI buffer + line/inst select relay 2026-05-30 19:56:55 -05:00
stage2_dac.erc PM_K-1 hardware: resolve TQ2SA relay pinout; Stage 2 DAC + reconstruction filter 2026-05-30 20:06:26 -05:00
stage2_dac.log PM_K-1 hardware: resolve TQ2SA relay pinout; Stage 2 DAC + reconstruction filter 2026-05-30 20:06:26 -05:00
stage2_dac_sklib.py PM_K-1 hardware: resolve TQ2SA relay pinout; Stage 2 DAC + reconstruction filter 2026-05-30 20:06:26 -05:00
stage3_sum.erc PM_K-1 hardware: Stage 3 -- summing node (selected input + click) 2026-05-30 20:15:17 -05:00
stage3_sum.log PM_K-1 hardware: Stage 3 -- summing node (selected input + click) 2026-05-30 20:15:17 -05:00
stage3_sum_sklib.py PM_K-1 hardware: Stage 3 -- summing node (selected input + click) 2026-05-30 20:15:17 -05:00
stage4_driver.erc PM_K-1 hardware: Stage 4 -- balanced output driver (completes the audio chain) 2026-05-30 20:27:04 -05:00
stage4_driver.log PM_K-1 hardware: Stage 4 -- balanced output driver (completes the audio chain) 2026-05-30 20:27:04 -05:00
stage4_driver_sklib.py PM_K-1 hardware: Stage 4 -- balanced output driver (completes the audio chain) 2026-05-30 20:27:04 -05:00