metronome/hardware/LAYOUT.md

PM_K-1 Core Board — PCB Layout Guide

The rulebook for turning hardware/kicad/board.net (167 components) into a routed board. Read alongside pcb_layout_tutorial.md (how the tool works) and DESIGN.md (why the circuit is shaped this way). This is a mixed-signal board — a switching supply, sensitive ±15 V analog, a fast MCU, and USB all on one PCB — so layout discipline matters more than on a simple digital board. The schematic is done and verified; good layout is now what makes it actually perform.

1. Stackup — use 4 layers

A 2-layer board will work electrically but will be noisy. Use 4 layers:

L1  signal + components        (top)
L2  GROUND plane (solid)       <- the single most important thing for noise
L3  power (3V3 / +5 / ±15 split zones)
L4  signal + components        (bottom)

A solid ground plane directly under the signal layer gives every fast/analog trace a clean return path. Do not cut the L2 ground plane up (one exception: the star-point, below). Finish: ENIG (gold) — heirloom requirement.

2. Grounding — the heart of a mixed-signal board

There are three "kinds" of ground current that must not share copper:

• Switcher ground — the TPS65131 boost/inverter pumps current in sharp pulses. Dirty.
• Digital ground — RP2350, flash, USB. Medium.
• Analog ground — the ±15 V audio section (THAT/OPA, DAC). Must stay quiet.

Strategy: one solid ground plane (L2), but partition by placement — put the switcher in one corner, digital in another, analog in a third, so each section's return currents stay local and don't flow under another section. Join them at a single star point near the main ground entry. Keep the switcher's high-current loop entirely in its corner.

• AGND (analog signal ground) and CHASSIS (shield) meet only through the ground-lift relay K3 + its 100 Ω∥10 nF soft-lift — keep those two nodes otherwise separate.
• The DAC datasheet rule: AGND/DGND/CPGND within 0.2 V of each other — tie them at the star.

3. Switching supply (TPS65131) — most layout-critical block

Switchers fail in layout, not schematic. Keep these loops physically tiny:

• Input caps (C1/C2, 4.7 µF) right at the INP/INN pins.
• Inductors L1/L2 (4.7 µH) and Schottkys D1/D2 (MBRM120) close to the switch nodes (SW_BOOST, SW_INV) — these nodes are the noisiest copper on the board; keep them small and away from everything analog. Don't run any audio or USB trace near them.
• Output caps (C4/C5, 22 µF) close to VPOS/VNEG.
• Feedback dividers (R1/R2, R3/R4) and VREF (C8) routed quietly, away from the switch nodes.
• Then the ±15 V LDOs (TPS7A49/30) take the raw ±18 V to clean rails — place them between the switcher and the analog section so the clean rails enter analog, not the raw ones.

4. Analog audio section — keep it quiet and far

• Place the whole audio chain (THAT1240/1646, OPA1641/1612, DAC, relays) as a group, far from the switcher and the digital ribbon.
• No analog audio trace runs parallel to the fast SPI or the switch nodes (this is why the analog interconnect J3 is physically separate from the digital ribbon J2).
• Film coupling caps and 0.1 % resistors in the signal path; keep signal traces short.
• The balanced in/out: route HOT/COLD as a tight pair so noise hits both equally (that's what the receiver's CMRR rejects). The MUTE (K2) and GND-LIFT (K3) relays near the output.
• The level-cal trimmer RV1 must be reachable with a screwdriver after assembly.

5. RP2350 core (per RP "Hardware design with RP2350")

• QSPI flash (U?) traces to the RP2350 short and direct — high-frequency bus.
• 12 MHz crystal tight to XIN/XOUT, with its own local ground; a guard ring helps; keep fast signals away from underneath it.
• Core SMPS: the 3.3 µH inductor loop (VREG_LX → DVDD) small; 100 nF per power pin, placed right at each pin.
• BOOTSEL (R6 1 k + button) and the flash-CS resistors close to the flash.

6. USB

• D+/D- (USB_DP_CONN/USB_DM_CONN) routed as a 90 Ω differential pair: short, length-matched, same layer, reference the ground plane, no stubs.
• The USBLC6-2 ESD and the 27 Ω series resistors right at the connector, before the pair.
• CC 5.1 k pulldowns near the connector. USB-C shell to chassis.

7. The two interconnects (the modular split)

• J2 digital ribbon (Pico-pinout) and J3 analog (balanced audio + speaker) are on separate connectors on purpose — keep them physically apart on the board and in the cabling. Interleave grounds on the digital ribbon for the SPI return.
• J4 MIDI only matters if the DNP MIDI block is fitted.

8. Mechanical & fab

• 4× M3 mounting holes with keep-outs; a chassis-ground pad.
• USB-C connector with through-hole anchor tabs (SMD-only tabs shear off — unacceptable for a 50-year device). Connector strain relief lives on the face/enclosure.
• Shrouded/keyed/latching interconnect headers.
• 4-layer, ENIG, controlled impedance on the USB pair. Optional conformal coat for humidity.

9. Thermal

• The ±15 V LDOs dissipate (Vin−Vout)×I ≈ (18−15)×~30 mA ≈ 90 mW each — small, but give them copper pour / the PowerPAD to the plane.
• The TPS65131 thermal pad to the ground plane with vias.

10. Do-not-populate (DNP) blocks

Per form factor, these are optional — leave the footprints, populate per build:

• MIDI (U?/H11L1 opto + 74LVC14 buffer + its resistors)
• SIG/CLIP indicator (LM393 + peak-detect parts)
• monitor speaker amp (PAM8302A + its caps/resistors) The BOM flags the DNP ICs; their surrounding passives are DNP too when the block is unfitted.

11. Pre-fab confirm list (flagged during capture)

• Footprints: RV-8803-C7, the QFN variants (RP2350A/TPS65131), USB-C (24-pin symbol vs the 16-pin GCT USB4085 part — pick one), the relay TQ2-SA.
• Values: LDO V_FB exact (used 1.194 V / −1.18 V for the dividers); crystal load caps (~15 pF per the chosen crystal); 3.3 V-MIDI series-R values.
• Confirm: H11L1 pinout (standard; datasheet fetch had timed out); PCM5102A MCLK-less = SCK→GND.

12. Final checks before Gerbers

1. DRC clean (clearances, track widths, the diff-pair rules).
2. Re-import the netlist and confirm no unrouted nets (ratsnest empty).
3. Verify the switcher loops are tight and isolated; analog has no switch-node neighbors.
4. Confirm the ground star point and the analog/digital partition.
5. Generate Gerbers + drill + pick-and-place + the BOM (BOM_board.csv) for the fab.