2 commits

Author	SHA1	Message	Date
Me Here	88af54e544	PM_K-1 hardware: fix footprint names so board.net imports cleanly into KiCad ... Audited every footprint in board.net against the KiCad 9 libraries: 6 were wrong names, now corrected to the real library footprints: - QFN-24 -> ..._EP2.65x2.65mm (TPS65131); QFN-60 -> ..._EP3.4x3.4mm (RP2350A) - HVSSOP-8 -> ..._EP1.57x1.89mm (LDOs); SOIC-8 wide -> 5.3x5.3mm (W25Q128) - Keystone 1066 -> 1060 holder; inductor -> L_1210_3225Metric placeholder (set per part) Now 25/27 footprints resolve; only RV-8803-C7 and the TQ2SA relay need custom footprints (KiCad has neither) -- import from SnapEDA/manufacturer at layout. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>	2026-05-31 15:41:04 -05:00
Me Here	47edf4eb2a	PM_K-1 hardware: FULL-BOARD integration -- single master netlist (board.py) ... circuits/board.py re-implements every block (power tree, RP2350 core, audio chain, RTC, MIDI-DNP, interconnects, SIG/CLIP-DNP, speaker-DNP) with shared net objects and SKiDL auto-assigned reference designators -> one coherent board.net for PCB layout. 167 components, unique refs U1-U18 / K1-K3 / J1-J5. ERC 0 errors; netlist 0 errors. Remaining ERC warnings are all benign unconnected-pin notes on intentionally-spare pins (relay NO contacts, 4 unused ULN2003 channels, spare GPIOs, 2 unused 74LVC14 inverters, RTC CLKOUT, TPS65131 BSW) and OC<->GPIO notes (comparator/opto outputs read by the MCU). MCLK-less: PCM5102A SCK tied to GND (internal PLL). This is the complete schematic deliverable: board.net + BOM.csv ready for layout. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>	2026-05-30 23:56:42 -05:00