- gen_bom.py + BOM_board.csv: authoritative BOM generated from board.net (70 line items,
167 placements), grouped with MPNs; refs match the integrated netlist; DNP ICs flagged.
(Supersedes the early hand-written BOM.csv, which used per-block refs.)
- LAYOUT.md: routing rulebook for board.net -- 4-layer stackup, the grounding/star-point
strategy, switcher loop isolation, analog separation, USB diff pair, RP2350/crystal/flash,
thermal, DNP blocks, pre-fab confirm list, DRC checklist.
- pcb_layout_tutorial.md: beginner orientation -- use KiCad; the schematic/netlist=contract
vs layout=physical-realization paradigm; the import->place->route->pour->DRC->Gerber
workflow; vocabulary; how our files fit; learning resources; honest expectations.
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
The committed indicator.py errored (UnboundLocalError: p15) -- an augmented assign on a
global Net inside threshold() made it local. Flipped to rt[1]+=p15. Now ERC 0 / netlist 0.
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
circuits/midi.py, a do-not-populate option (USB-MIDI is the default). H11L1 opto-isolated
IN (breaks the MIDI ground loop), 74LVC14-buffered OUT (TX through two inverters) and THRU
(re-buffered IN). Connector is a face choice; core exposes the loop nets MIDI_IN/OUT/THRU_A/B
plus MIDI_TX/RX to the RP2350 UART. ERC 0 errors; netlist 0 errors.
CONFIRM: H11L1 pinout (standard; datasheet fetch timed out) + 3.3V-MIDI series-R values.
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
These build outputs leaked into git (the .gitignore only covered .net/.pdf/etc). Added
the patterns and untracked the files (kept on disk). Keeps the repo to source only and
stops generated churn from being swept into unrelated commits.
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Diagnosed from the user's console output - 25 chunks pushed cleanly at
~124ms each, then stalled. Two coupled causes:
1) Bus contention. tick() and Live sync share self.midi with the chunk
ACKs. While the device was processing a chunk, a Note On / Clock Out /
Live-sync FULL heartbeat could land on the same MIDI OUT stream and
the host's parser dropped the interleaved ACK SysEx.
Fix: self._fw_pushing flag set on 0x21 BEGIN, cleared on 0x23 COMMIT
or any error. midi_send / Clock Out / _sync_broadcast / _sync_broadcast_full
all early-out when _fw_pushing is True. Only ACKs go out during a push.
2) SysEx assembler garbage. self._sx = bytearray() per chunk leaks ~70
bytes / chunk that only GC'd every 50 chunks. 25 chunks of trash plus a
slow heap walked the wrong way explains the ramp-up to 174 -> 119 -> 124
ms ACK times. GC every chunk now (~30ms cost on RP2040/RP2350 with
small heap) so the assembler buffer is always fresh.
Same patch on both pico-cp/ and pico-explorer/ since the bug is identical.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
circuits/power_tree.py captures the full supply, topology + values verified from the
TPS65131 datasheet (SLVS493E: pinout p3, Typical Application Fig 8-1 p11, BOM Table 8-2
p12, FB equations p13 Vref=1.213V) and the TPS7A49/TPS7A30 LDO datasheets:
- TPS65131 dual boost/inverter: L1/L2=4.7uH, D1/D2=MBRM120, FB dividers set ~+/-18.2V
(R1=1.4M/R2=100k, R3=1.5M/R4=100k), comp C7/C6 on CP/CN, VREF 220nF, no Q1 (USB),
PSP/PSN=GND forced-PWM for low audio-band noise.
- TPS7A4901/TPS7A3001 post-regulate to clean +/-15V (shared 8-pin pinout, EN tied to IN).
- AP2112K-3.3 -> digital 3V3.
ERC 0 errors; netlist 0 errors.
CONFIRM before fab: exact LDO Vfb (used ~1.194V/-1.18V for the dividers) and the
AP2112K SOT-23-5 pinout. Switcher validated vs TI reference design; no SPICE (behavioral
models don't validate a switcher) -- layout per the TI EVM.
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
circuits/audio_chain.py wires stages 1/1b/2/3/4 with shared nets and deduplicated
parts: ONE OPA1612 (U4) does both the Stage-2 filter (A) and Stage-3 summer (B);
ONE ULN2003 (U6) drives all three relays (K1 select, K2 mute, K3 ground-lift).
54 components, ERC 0 errors, netlist 0 errors. Per-stage files remain as the
documented, individually-simulated building blocks.
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
THAT1646 balanced driver (pinout verified, THAT doc 600078 rev07) closes the chain:
MIX_OUT -> 25-turn level-cal trim -> THAT1646 (+6dB, sense tied local) -> 47ohm
build-out -> fail-safe mute relay K2 -> balanced AOUT_HOT/COLD on the interconnect;
ground-lift relay K3 (de-energized=bonded, soft-lift 100R||10nF) -> CHASSIS.
- Phase: Stage 3 inversion corrected via HOT<-OUT-, COLD<-OUT+.
- Level cal trim ahead of the driver (its +6dB gain is fixed).
- K2 fail-safe: de-energized shorts both legs to GND after the build-out (driver
current-limited). K3 ground-lift in series with a face panel switch.
- stage4_driver.cir: differential flat +4.76dB (1k=20k), legs antiphase (0 vs pi rad),
build-out+cable rolloff above audio. ERC 0 errors; netlist 0 errors.
AUDIO CHAIN COMPLETE: stages 1, 1b, 2, 3, 4 all captured + simulated + ERC-clean.
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Inverting summing amp (OPA1612 section) mixes STAGE1_OUT (line/instrument) and
CLICK_OUT (filtered DAC) at unity into MIX_OUT. Each source enters its own 10k into
the op-amp virtual ground, so they sum with no interaction.
stage3_sum.cir confirms: each input alone = 0 dB, both together = +6.02 dB, and each
input's gain is unchanged by the other (virtual-ground isolation). ERC/netlist 0 errors.
Note: inverting summer flips phase -> corrected at the Stage 4 balanced driver via
hot/cold assignment. At integration, this summer can use the parked 2nd half of the
Stage 2 filter OPA1612 (U4) instead of a separate package.
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
OPA1641 non-inverting DI buffer (1Mohm in, +12dB) + TQ2SA DPDT relay that both
routes the jack tip (line receiver vs DI buffer) and selects the output. Default
de-energized = LINE (common case, fail-safe). Driven by the shared ULN2003 via
net K1_DRV from GPIO SEL_LINST.
Pinouts verified from datasheets before capture (per the no-guessing rule):
- OPA1641 (TI SBOS484D): 1=NC 2=-IN 3=+IN 4=V- 5=NC 6=OUT 7=V+ 8=NC.
- ULN2003A: GND=8, COM=9, in 1-7 / out 16-10.
- TQ2SA (Panasonic TQ-SMD): pole1 COM=3 throws 2/4, pole2 COM=8 throws 7/9
(from contact-resistance terminal pairs). NC/NO orientation + coil pins (1/10)
follow the standard single-side-stable diagram -- flagged in-file for a final
connection-diagram cross-check (not over-claimed).
ngspice stage1b_di.cir confirms +12.04dB gain, flat across the audio band.
ERC 0 errors; netlist 0 errors.
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Verified the receiver from THAT doc 600035 rev05 instead of guessing:
- THAT1240 = 0 dB (unity) -- correct as specced; 1243=-3dB, 1246=-6dB would be wrong.
- SO-8 pinout 1=Ref 2=In- 3=In+ 4=Vee 5=Sense 6=Vout 7=Vcc 8=NC. My initial
SKiDL pins were mostly wrong; corrected. Netlist now matches the datasheet.
- KiCad Device:D is pin1=K/pin2=A; my clamp diodes were reversed -- fixed so they
actually clamp (D high->cathode to +15, D low->anode to -15).
- BOM part numbers had a bogus "W16" suffix; corrected to S08-U (SO-8). Noted
INA134/SSM2141 as pin-compatible 2nd sources for long-term availability.
ERC 0 errors, netlist 0 errors.
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Capture method = SKiDL per decision. circuits/stage1_input.py defines the
balanced line receiver + per-leg protection (DC-block film cap, series R, bias R,
clamp diodes to the rails) and emits a KiCad netlist. ERC: 0 errors (2 expected
warnings -- AIN_HOT/COLD reach only one pin until the interconnect block exists).
Container: env vars point SKiDL/KiCad at the symbol/footprint libs.
VERIFY-before-layout flagged in-file: exact THAT124x gain suffix, its SO-8 pin
numbers, clamp-diode orientation.
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Audio chain, stage 1 (balanced input receiver + protection) validated in ngspice:
- stage1_cmrr.cir: CMRR vs resistor matching -> 1% = 46dB, 0.1% = 66dB, perfect
= amp-limited; justifies the laser-trimmed THAT1240 over discrete resistors.
- stage1_phantom.cir: +48V phantom step -> clamped to ~16V blip, steady-state
~0.12V; the DC-block cap + clamp + series R make a miswire a non-event.
Container: add kicad-symbols + kicad-footprints (for symbol placement) and skidl.
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Pinned toolchain under hardware/eda/ so the design can be checked/simulated
identically in the future (system KiCad is 7.0, which has no CLI ERC):
- Containerfile: Ubuntu 24.04 + KiCad 9 (PPA) + ngspice + python3.
- run.sh: build-if-needed + run with the repo mounted; lands in hardware/kicad.
- sim/input_loading.cir: ngspice deck proving the line(25k) vs instrument(1M)
input-loading decision — Hi-Z preserves a +16dB pickup resonance the 25k load
flattens to -3dB.
Verified: KiCad 9.0.9, ngspice-42, ERC runs clean (0 violations) on
pm_k1_core.kicad_sch.
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
