617bb5a8b2
circuits/audio_chain.py wires stages 1/1b/2/3/4 with shared nets and deduplicated parts: ONE OPA1612 (U4) does both the Stage-2 filter (A) and Stage-3 summer (B); ONE ULN2003 (U6) drives all three relays (K1 select, K2 mute, K3 ground-lift). 54 components, ERC 0 errors, netlist 0 errors. Per-stage files remain as the documented, individually-simulated building blocks. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
195 lines
11 KiB
Python
195 lines
11 KiB
Python
#!/usr/bin/env python3
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"""PM_K-1 audio chain - INTEGRATED board netlist (SKiDL).
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Wires stages 1, 1b, 2, 3, 4 into one netlist with shared nets and DEDUPLICATED parts:
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* the Stage-2 reconstruction filter and the Stage-3 summer share ONE OPA1612 dual
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(U4: section A = filter, section B = summer) -- no parked half.
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* the three relays (K1 select, K2 mute, K3 ground-lift) share ONE ULN2003 (U6).
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This is the source of truth for the integrated audio netlist; the per-stage circuits/
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files remain as the documented, individually-simulated building blocks.
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Run INSIDE the EDA container:
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cd hardware/eda && ./run.sh python3 ../eda/circuits/audio_chain.py
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Outputs ERC + hardware/kicad/audio_chain.net.
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All IC pinouts datasheet-verified (see the per-stage files for the citations):
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THAT1240 1=Ref 2=In- 3=In+ 4=Vee 5=Sns 6=Vout 7=Vcc 8=NC
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OPA1641 1=NC 2=-IN 3=+IN 4=V- 5=NC 6=OUT 7=V+ 8=NC
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OPA1612 1=OUTA 2=-INA 3=+INA 4=V- 5=+INB 6=-INB 7=OUTB 8=V+
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PCM5102A (TSSOP-20) per TI SLAS859C
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THAT1646 1=Out- 2=Sns- 3=Gnd 4=In 5=Vee 6=Vcc 7=Sns+ 8=Out+
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TQ2SA coil 1/10; pole1 COM3/NC4/NO2; pole2 COM8/NC7/NO9
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ULN2003A in 1B-7B=1..7, out 1C-7C=16..10, GND=8, COM=9
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"""
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import os
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from skidl import *
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set_default_tool(KICAD9)
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R = Part("Device", "R", dest=TEMPLATE, footprint="Resistor_SMD:R_0805_2012Metric")
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C = Part("Device", "C", dest=TEMPLATE, footprint="Capacitor_SMD:C_0805_2012Metric")
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D = Part("Device", "D", dest=TEMPLATE, footprint="Diode_SMD:D_SOD-323")
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# ---------------- nets ----------------
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p15, n15, p3v3, p5, gnd = Net("+15V"), Net("-15V"), Net("+3V3"), Net("+5V"), Net("GND")
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for n in (p15, n15, p3v3, p5, gnd):
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n.drive = POWER
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# audio signal flow
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ain_hot, ain_cold = Net("AIN_HOT"), Net("AIN_COLD") # input jack tip/ring
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rx_hot_in = Net("RX_HOT_IN") # relay-routed hot -> receiver
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rx_out, di_in, di_out = Net("RX_OUT"), Net("DI_IN"), Net("DI_OUT")
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stage1_out, click_out, mix_out = Net("STAGE1_OUT"), Net("CLICK_OUT"), Net("MIX_OUT")
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aout_hot, aout_cold, chassis = Net("AOUT_HOT"), Net("AOUT_COLD"), Net("CHASSIS")
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# DAC clocks/data + control
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mclk, i2s_bck, i2s_din, i2s_lrck = Net("MCLK"), Net("I2S_BCK"), Net("I2S_DIN"), Net("I2S_LRCK")
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dac_xsmt = Net("DAC_XSMT")
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sel_linst, mute_en, gndlift_en = Net("SEL_LINST"), Net("MUTE_EN"), Net("GNDLIFT_EN")
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k1_drv, k2_drv, k3_drv = Net("K1_DRV"), Net("K2_DRV"), Net("K3_DRV")
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# ---------------- part definitions ----------------
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def mk(name, pins, ref_prefix="U", fp="Package_SO:SOIC-8_3.9x4.9mm_P1.27mm"):
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return Part(name=name, tool=SKIDL, dest=TEMPLATE, ref_prefix=ref_prefix, footprint=fp, pins=pins)
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P = Pin.types
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THAT1240 = mk("THAT1240", [Pin(num=1,name="REF",func=P.INPUT),Pin(num=2,name="IN-",func=P.INPUT),
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Pin(num=3,name="IN+",func=P.INPUT),Pin(num=4,name="V-",func=P.PWRIN),Pin(num=5,name="SENSE",func=P.PASSIVE),
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Pin(num=6,name="OUT",func=P.OUTPUT),Pin(num=7,name="V+",func=P.PWRIN),Pin(num=8,name="NC",func=P.NOCONNECT)])
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OPA1641 = mk("OPA1641", [Pin(num=1,name="NC1",func=P.NOCONNECT),Pin(num=2,name="-IN",func=P.INPUT),
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Pin(num=3,name="+IN",func=P.INPUT),Pin(num=4,name="V-",func=P.PWRIN),Pin(num=5,name="NC5",func=P.NOCONNECT),
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Pin(num=6,name="OUT",func=P.OUTPUT),Pin(num=7,name="V+",func=P.PWRIN),Pin(num=8,name="NC8",func=P.NOCONNECT)])
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OPA1612 = mk("OPA1612", [Pin(num=1,name="OUTA",func=P.OUTPUT),Pin(num=2,name="-INA",func=P.INPUT),
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Pin(num=3,name="+INA",func=P.INPUT),Pin(num=4,name="V-",func=P.PWRIN),Pin(num=5,name="+INB",func=P.INPUT),
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Pin(num=6,name="-INB",func=P.INPUT),Pin(num=7,name="OUTB",func=P.OUTPUT),Pin(num=8,name="V+",func=P.PWRIN)])
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THAT1646 = mk("THAT1646", [Pin(num=1,name="OUT-",func=P.OUTPUT),Pin(num=2,name="SNS-",func=P.INPUT),
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Pin(num=3,name="GND",func=P.PWRIN),Pin(num=4,name="IN",func=P.INPUT),Pin(num=5,name="V-",func=P.PWRIN),
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Pin(num=6,name="V+",func=P.PWRIN),Pin(num=7,name="SNS+",func=P.INPUT),Pin(num=8,name="OUT+",func=P.OUTPUT)])
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PCM5102A = mk("PCM5102A", [Pin(num=1,name="CPVDD",func=P.PWRIN),Pin(num=2,name="CAPP",func=P.PASSIVE),
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Pin(num=3,name="CPGND",func=P.PWRIN),Pin(num=4,name="CAPM",func=P.PASSIVE),Pin(num=5,name="VNEG",func=P.PASSIVE),
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Pin(num=6,name="OUTL",func=P.OUTPUT),Pin(num=7,name="OUTR",func=P.OUTPUT),Pin(num=8,name="AVDD",func=P.PWRIN),
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Pin(num=9,name="AGND",func=P.PWRIN),Pin(num=10,name="DEMP",func=P.INPUT),Pin(num=11,name="FLT",func=P.INPUT),
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Pin(num=12,name="SCK",func=P.INPUT),Pin(num=13,name="BCK",func=P.INPUT),Pin(num=14,name="DIN",func=P.INPUT),
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Pin(num=15,name="LRCK",func=P.INPUT),Pin(num=16,name="FMT",func=P.INPUT),Pin(num=17,name="XSMT",func=P.INPUT),
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Pin(num=18,name="LDOO",func=P.PWROUT),Pin(num=19,name="DGND",func=P.PWRIN),Pin(num=20,name="DVDD",func=P.PWRIN)],
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fp="Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm")
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TQ2SA = mk("TQ2SA-5V", [Pin(num=1,name="COIL_A",func=P.PASSIVE),Pin(num=10,name="COIL_B",func=P.PASSIVE),
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Pin(num=3,name="P1_COM",func=P.PASSIVE),Pin(num=4,name="P1_NC",func=P.PASSIVE),Pin(num=2,name="P1_NO",func=P.PASSIVE),
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Pin(num=8,name="P2_COM",func=P.PASSIVE),Pin(num=7,name="P2_NC",func=P.PASSIVE),Pin(num=9,name="P2_NO",func=P.PASSIVE),
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Pin(num=5,name="NC5",func=P.NOCONNECT),Pin(num=6,name="NC6",func=P.NOCONNECT)],
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ref_prefix="K", fp="Relay_SMD:Relay_DPDT_Panasonic_TQ2-SA")
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ULN2003 = mk("ULN2003A", [Pin(num=1,name="1B",func=P.INPUT),Pin(num=2,name="2B",func=P.INPUT),
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Pin(num=3,name="3B",func=P.INPUT),Pin(num=4,name="4B",func=P.INPUT),Pin(num=5,name="5B",func=P.INPUT),
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Pin(num=6,name="6B",func=P.INPUT),Pin(num=7,name="7B",func=P.INPUT),Pin(num=8,name="GND",func=P.PWRIN),
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Pin(num=9,name="COM",func=P.PWRIN),Pin(num=10,name="7C",func=P.OPENCOLL),Pin(num=11,name="6C",func=P.OPENCOLL),
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Pin(num=12,name="5C",func=P.OPENCOLL),Pin(num=13,name="4C",func=P.OPENCOLL),Pin(num=14,name="3C",func=P.OPENCOLL),
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Pin(num=15,name="2C",func=P.OPENCOLL),Pin(num=16,name="1C",func=P.OPENCOLL)],
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fp="Package_SO:SOIC-16_3.9x9.9mm_P1.27mm")
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# instances (deduplicated)
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u1 = THAT1240(ref="U1") # line receiver
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u2 = OPA1641(ref="U2") # Hi-Z DI buffer
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u3 = PCM5102A(ref="U3") # DAC
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u4 = OPA1612(ref="U4") # A = recon filter, B = summer (shared dual)
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u5 = THAT1646(ref="U5") # balanced driver
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u6 = ULN2003(ref="U6") # shared relay driver
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k1, k2, k3 = TQ2SA(ref="K1"), TQ2SA(ref="K2"), TQ2SA(ref="K3")
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def dcp(rail): # 100nF decoupling helper
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c = C(value="100nF"); rail += c[1]; c[2] += gnd
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# ---------------- Stage 1: balanced line receiver + protection ----------------
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def protect_bal(src, tag):
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cblk = C(value="2.2uF", footprint="Capacitor_SMD:C_1206_3216Metric")
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rs, rb = R(value="1k"), R(value="1Meg")
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dp, dn = D(value="1N4148WS"), D(value="1N4148WS")
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node = Net(tag)
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src += cblk[1]; cblk[2] += rs[1]; rs[2] += node
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rb[1] += node; rb[2] += gnd
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dp[1] += p15; dp[2] += node # Device:D pin1=K,pin2=A : high clamp
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dn[1] += node; dn[2] += n15 # low clamp
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return node
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u1["IN+"] += protect_bal(rx_hot_in, "RXIN_P") # hot comes from the select relay (NC)
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u1["IN-"] += protect_bal(ain_cold, "RXIN_N") # cold is the ring (direct)
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u1["REF"] += gnd; u1["SENSE"] += rx_out; u1["OUT"] += rx_out
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u1["V+"] += p15; u1["V-"] += n15; dcp(p15); dcp(n15)
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# ---------------- Stage 1b: Hi-Z DI buffer (OPA1641) ----------------
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cblk = C(value="100nF", footprint="Capacitor_SMD:C_1206_3216Metric")
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rbias = R(value="1Meg"); dp, dn = D(value="1N4148WS"), D(value="1N4148WS")
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di_node = Net("DI_NODE")
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di_in += cblk[1]; cblk[2] += di_node
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rbias[1] += di_node; rbias[2] += gnd
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dp[1] += p15; dp[2] += di_node
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dn[1] += di_node; dn[2] += n15
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u2["+IN"] += di_node
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rf2, rg2 = R(value="3k"), R(value="1k") # +12 dB
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u2["OUT"] += di_out
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rf2[1] += di_out; rf2[2] += u2["-IN"]
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rg2[1] += u2["-IN"]; rg2[2] += gnd
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u2["V+"] += p15; u2["V-"] += n15; dcp(p15); dcp(n15)
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# ---------------- Stage 1b: select relay K1 ----------------
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k1["P1_COM"] += ain_hot; k1["P1_NC"] += rx_hot_in; k1["P1_NO"] += di_in # route tip
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k1["P2_COM"] += stage1_out; k1["P2_NC"] += rx_out; k1["P2_NO"] += di_out # select output
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k1["COIL_A"] += p5; k1["COIL_B"] += k1_drv
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# ---------------- Stage 2: PCM5102A DAC ----------------
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for pin in ("AVDD","CPVDD","DVDD"): u3[pin] += p3v3
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for pin in ("AGND","DGND","CPGND"): u3[pin] += gnd
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for pin in ("AVDD","CPVDD","DVDD"):
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c = C(value="100nF"); u3[pin] += c[1]; c[2] += gnd
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cb = C(value="10uF", footprint="Capacitor_SMD:C_1206_3216Metric"); u3["AVDD"] += cb[1]; cb[2] += gnd
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cfly = C(value="2.2uF"); u3["CAPP"] += cfly[1]; u3["CAPM"] += cfly[2]
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cvneg = C(value="2.2uF"); u3["VNEG"] += cvneg[1]; cvneg[2] += gnd
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cldoo = C(value="1uF"); u3["LDOO"] += cldoo[1]; cldoo[2] += gnd
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u3["DEMP"] += gnd; u3["FLT"] += gnd; u3["FMT"] += gnd
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u3["XSMT"] += dac_xsmt; rpu = R(value="10k"); dac_xsmt += rpu[1]; rpu[2] += p3v3
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u3["SCK"] += mclk; u3["BCK"] += i2s_bck; u3["DIN"] += i2s_din; u3["LRCK"] += i2s_lrck
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rload = R(value="2.2k"); u3["OUTR"] += rload[1]; rload[2] += gnd
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# ---------------- Stage 2: reconstruction filter = OPA1612 section A ----------------
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r1, r2 = R(value="1.5k"), R(value="1.5k"); ca = C(value="2.2nF"); cbq = C(value="1nF")
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rcA = Net("RC_A")
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u3["OUTL"] += r1[1]; r1[2] += rcA
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r2[1] += rcA; r2[2] += u4["+INA"]
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ca[1] += rcA; ca[2] += u4["OUTA"]
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cbq[1] += u4["+INA"]; cbq[2] += gnd
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u4["-INA"] += u4["OUTA"]; u4["OUTA"] += click_out
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u4["V+"] += p15; u4["V-"] += n15; dcp(p15); dcp(n15)
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# ---------------- Stage 3: summer = OPA1612 section B (shared chip) ----------------
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ri_in, ri_clk, rf3 = R(value="10k"), R(value="10k"), R(value="10k")
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stage1_out += ri_in[1]; ri_in[2] += u4["-INB"]
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click_out += ri_clk[1]; ri_clk[2] += u4["-INB"]
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rf3[1] += u4["-INB"]; rf3[2] += u4["OUTB"]
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u4["+INB"] += gnd; u4["OUTB"] += mix_out
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# ---------------- Stage 4: level trim + THAT1646 + build-out ----------------
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RV = Part("Device","R_Potentiometer", dest=TEMPLATE,
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footprint="Potentiometer_THT:Potentiometer_Bourns_3296W_Vertical")
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rv1 = RV(value="10k", ref="RV1")
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mix_out += rv1[1]; rv1[3] += gnd; rv1[2] += u5["IN"]
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u5["SNS-"] += u5["OUT-"]; u5["SNS+"] += u5["OUT+"]; u5["GND"] += gnd
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u5["V+"] += p15; u5["V-"] += n15; dcp(p15); dcp(n15)
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rbo_h, rbo_c = R(value="47"), R(value="47")
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u5["OUT-"] += rbo_h[1]; rbo_h[2] += aout_hot # phase-corrected: HOT<-OUT-
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u5["OUT+"] += rbo_c[1]; rbo_c[2] += aout_cold # COLD<-OUT+
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# ---------------- Stage 4: mute relay K2 + ground-lift relay K3 ----------------
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k2["P1_COM"] += aout_hot; k2["P1_NC"] += gnd # de-energized = muted (short to gnd)
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k2["P2_COM"] += aout_cold; k2["P2_NC"] += gnd
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k2["COIL_A"] += p5; k2["COIL_B"] += k2_drv
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k3["P1_COM"] += gnd; k3["P1_NC"] += chassis # de-energized = bonded
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rlift = R(value="100"); clift = C(value="10nF")
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rlift[1] += gnd; rlift[2] += chassis; clift[1] += gnd; clift[2] += chassis
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k3["COIL_A"] += p5; k3["COIL_B"] += k3_drv
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# ---------------- shared relay driver U6 (ULN2003): 3 channels ----------------
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u6["1B"] += sel_linst; u6["1C"] += k1_drv
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u6["2B"] += mute_en; u6["2C"] += k2_drv
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u6["3B"] += gndlift_en; u6["3C"] += k3_drv
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u6["GND"] += gnd; u6["COM"] += p5 # flyback common to coil supply
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ERC()
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out = os.path.abspath(os.path.join(os.path.dirname(__file__), "..", "..", "kicad", "audio_chain.net"))
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generate_netlist(file_=out)
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print("Integrated audio netlist ->", out)
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