8f662598e4
circuits/midi.py, a do-not-populate option (USB-MIDI is the default). H11L1 opto-isolated IN (breaks the MIDI ground loop), 74LVC14-buffered OUT (TX through two inverters) and THRU (re-buffered IN). Connector is a face choice; core exposes the loop nets MIDI_IN/OUT/THRU_A/B plus MIDI_TX/RX to the RP2350 UART. ERC 0 errors; netlist 0 errors. CONFIRM: H11L1 pinout (standard; datasheet fetch timed out) + 3.3V-MIDI series-R values. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
79 lines
4.3 KiB
Python
79 lines
4.3 KiB
Python
#!/usr/bin/env python3
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"""PM_K-1 MIDI block (SKiDL) -- DNP populate-option: opto-isolated IN + buffered OUT + THRU.
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Run INSIDE the EDA container:
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cd hardware/eda && ./run.sh python3 ../eda/circuits/midi.py
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Outputs ERC + hardware/kicad/midi.net.
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USB-MIDI is the DEFAULT (firmware). This hardware DIN/TRS MIDI is a DO-NOT-POPULATE
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option for laptop-free sync to standalone gear (a "stage" face fits the connector + parts).
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IN : opto-isolated (H11L1) -- breaks the ground loop the MIDI spec requires.
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OUT : RP2350 UART TX -> 74LVC14 buffer (2 inverters = non-inverting) -> series R.
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THRU: a buffered copy of the received IN signal (re-transmit), same buffer chip.
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PINOUTS
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* 74LVC14 hex Schmitt inverter: standard 14-pin (1A/1Y..6A/6Y, GND=7, VCC=14).
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* H11L1 6-pin Schmitt opto: standard 1=Anode 2=Cathode 3=NC 4=GND 5=VO 6=VCC
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(universal across makers of this part; datasheet fetch timed out -- reconfirm at layout).
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CONFIRM: the series-resistor values for 3.3V MIDI per the MIDI Association spec (placeholders
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below). Connector (TRS-MIDI Type-A vs DIN-5) is a FACE choice; the core exposes the loop nets.
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"""
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import os
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from skidl import *
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set_default_tool(KICAD9)
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P = Pin.types
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R = Part("Device","R", dest=TEMPLATE, footprint="Resistor_SMD:R_0402_1005Metric")
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def C(v): return Part("Device","C", value=v, footprint="Capacitor_SMD:C_0402_1005Metric")
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D = Part("Device","D", dest=TEMPLATE, footprint="Diode_SMD:D_SOD-323")
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p3v3, gnd = Net("+3V3"), Net("GND")
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p3v3.drive = POWER; gnd.drive = POWER
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midi_tx, midi_rx = Net("MIDI_TX"), Net("MIDI_RX") # to/from RP2350 UART (assign free GPIO at integ.)
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in_a, in_b = Net("MIDI_IN_A"), Net("MIDI_IN_B") # isolated current loop -> face connector
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out_a, out_b = Net("MIDI_OUT_A"), Net("MIDI_OUT_B")
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thru_a, thru_b = Net("MIDI_THRU_A"), Net("MIDI_THRU_B")
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OPTO = Part(name="H11L1", tool=SKIDL, dest=TEMPLATE, ref_prefix="U",
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footprint="Package_DIP:DIP-6_W7.62mm",
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pins=[Pin(num=1,name="A",func=P.PASSIVE),Pin(num=2,name="C",func=P.PASSIVE),Pin(num=3,name="NC",func=P.NOCONNECT),
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Pin(num=4,name="GND",func=P.PWRIN),Pin(num=5,name="VO",func=P.OPENCOLL),Pin(num=6,name="VCC",func=P.PWRIN)])
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BUF = Part(name="74LVC14", tool=SKIDL, dest=TEMPLATE, ref_prefix="U",
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footprint="Package_SO:TSSOP-14_4.4x5mm_P0.65mm",
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pins=[Pin(num=1,name="1A",func=P.INPUT),Pin(num=2,name="1Y",func=P.OUTPUT),Pin(num=3,name="2A",func=P.INPUT),
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Pin(num=4,name="2Y",func=P.OUTPUT),Pin(num=5,name="3A",func=P.INPUT),Pin(num=6,name="3Y",func=P.OUTPUT),
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Pin(num=7,name="GND",func=P.PWRIN),Pin(num=8,name="4Y",func=P.OUTPUT),Pin(num=9,name="4A",func=P.INPUT),
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Pin(num=10,name="5Y",func=P.OUTPUT),Pin(num=11,name="5A",func=P.INPUT),Pin(num=12,name="6Y",func=P.OUTPUT),
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Pin(num=13,name="6A",func=P.INPUT),Pin(num=14,name="VCC",func=P.PWRIN)])
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opto = OPTO(ref="U8"); buf = BUF(ref="U9")
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# ---- MIDI IN (opto-isolated) ----
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rin = R(value="220"); dprot = D(value="1N4148WS")
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in_a += rin[1]; rin[2] += opto["A"] # current-limit into LED
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opto["C"] += in_b # LED return (isolated side)
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dprot[2] += opto["C"]; dprot[1] += opto["A"] # reverse-protection across the LED (pin1=K,2=A)
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opto["VCC"] += p3v3; opto["GND"] += gnd
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rvo = R(value="10k"); opto["VO"] += midi_rx; midi_rx += rvo[1]; rvo[2] += p3v3 # pull-up; received data
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copt = C("100nF"); p3v3 += copt[1]; copt[2] += gnd
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# ---- MIDI OUT: TX -> two inverters -> series R ----
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buf["1A"] += midi_tx; buf["1Y"] += Net("MIDI_OUT_N") # first invert
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buf["2A"] += buf["1Y"] # second invert -> non-inverted
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ro_b = R(value="33"); buf["2Y"] += ro_b[1]; ro_b[2] += out_b
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ro_a = R(value="33"); p3v3 += ro_a[1]; ro_a[2] += out_a # current-source leg
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# ---- MIDI THRU: re-buffer the received signal ----
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buf["3A"] += midi_rx; buf["3Y"] += Net("MIDI_THRU_N")
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buf["4A"] += buf["3Y"]
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rt_b = R(value="33"); buf["4Y"] += rt_b[1]; rt_b[2] += thru_b
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rt_a = R(value="33"); p3v3 += rt_a[1]; rt_a[2] += thru_a
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# unused inverters parked, supply
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buf["5A"] += gnd; buf["6A"] += gnd
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buf["VCC"] += p3v3; buf["GND"] += gnd
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cbuf = C("100nF"); p3v3 += cbuf[1]; cbuf[2] += gnd
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ERC()
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out = os.path.abspath(os.path.join(os.path.dirname(__file__), "..", "..", "kicad", "midi.net"))
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generate_netlist(file_=out)
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print("MIDI netlist ->", out)
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