metronome/hardware/kicad
Me Here 6b6a58fa56 PM_K-1 hardware: Stage 3 -- summing node (selected input + click)
Inverting summing amp (OPA1612 section) mixes STAGE1_OUT (line/instrument) and
CLICK_OUT (filtered DAC) at unity into MIX_OUT. Each source enters its own 10k into
the op-amp virtual ground, so they sum with no interaction.

stage3_sum.cir confirms: each input alone = 0 dB, both together = +6.02 dB, and each
input's gain is unchanged by the other (virtual-ground isolation). ERC/netlist 0 errors.

Note: inverting summer flips phase -> corrected at the Stage 4 balanced driver via
hot/cold assignment. At integration, this summer can use the parked 2nd half of the
Stage 2 filter OPA1612 (U4) instead of a separate package.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
2026-05-30 20:15:17 -05:00
..
.gitignore PM_K-1 hardware: Stage 1 input receiver as SKiDL (code-defined schematic) 2026-05-30 19:43:07 -05:00
pm_k1_core.kicad_pro PM_K-1 hardware: core-board design-of-record + KiCad scaffold 2026-05-30 11:42:45 -05:00
pm_k1_core.kicad_sch PM_K-1 hardware: core-board design-of-record + KiCad scaffold 2026-05-30 11:42:45 -05:00
skidl.erc PM_K-1 hardware: Stage 1 input receiver as SKiDL (code-defined schematic) 2026-05-30 19:43:07 -05:00
skidl.log PM_K-1 hardware: Stage 1 input receiver as SKiDL (code-defined schematic) 2026-05-30 19:43:07 -05:00
skidl_REPL.erc PM_K-1 hardware: Stage 1 audio (input receiver) sims + container libs 2026-05-30 19:27:25 -05:00
skidl_REPL.log PM_K-1 hardware: Stage 1 audio (input receiver) sims + container libs 2026-05-30 19:27:25 -05:00
stage1_input.erc PM_K-1 hardware: Stage 1 input receiver as SKiDL (code-defined schematic) 2026-05-30 19:43:07 -05:00
stage1_input.log PM_K-1 hardware: verify THAT1240 against datasheet; fix pinout + part numbers 2026-05-30 19:48:41 -05:00
stage1_input_sklib.py PM_K-1 hardware: verify THAT1240 against datasheet; fix pinout + part numbers 2026-05-30 19:48:41 -05:00
stage1b_select.erc PM_K-1 hardware: Stage 1b -- Hi-Z instrument DI buffer + line/inst select relay 2026-05-30 19:56:55 -05:00
stage1b_select.log PM_K-1 hardware: Stage 1b -- Hi-Z instrument DI buffer + line/inst select relay 2026-05-30 19:56:55 -05:00
stage1b_select_sklib.py PM_K-1 hardware: Stage 1b -- Hi-Z instrument DI buffer + line/inst select relay 2026-05-30 19:56:55 -05:00
stage2_dac.erc PM_K-1 hardware: resolve TQ2SA relay pinout; Stage 2 DAC + reconstruction filter 2026-05-30 20:06:26 -05:00
stage2_dac.log PM_K-1 hardware: resolve TQ2SA relay pinout; Stage 2 DAC + reconstruction filter 2026-05-30 20:06:26 -05:00
stage2_dac_sklib.py PM_K-1 hardware: resolve TQ2SA relay pinout; Stage 2 DAC + reconstruction filter 2026-05-30 20:06:26 -05:00
stage3_sum.erc PM_K-1 hardware: Stage 3 -- summing node (selected input + click) 2026-05-30 20:15:17 -05:00
stage3_sum.log PM_K-1 hardware: Stage 3 -- summing node (selected input + click) 2026-05-30 20:15:17 -05:00
stage3_sum_sklib.py PM_K-1 hardware: Stage 3 -- summing node (selected input + click) 2026-05-30 20:15:17 -05:00