39fe087b2c
Added Node.js + netlistsvg to the EDA container; make_svg.py renders a SKiDL block to a schematic SVG. Generated hardware/eda/schematics/*.svg for 12 blocks (audio stages 1-4 + integrated, power tree, RP2350 core, RTC, MIDI, indicator, speaker) -- open in a browser. Auto-routed (functional, not pretty); per-block so they're readable. interconnect omitted (netlistsvg layout engine errors on the 24-pin USB-C + headers; its mapping is in DESIGN.md s7). Intermediates (.json/_skin.svg) git-ignored. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
14 lines
601 B
Python
14 lines
601 B
Python
#!/usr/bin/env python3
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"""Render one SKiDL block as a schematic SVG (via netlistsvg).
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Usage (inside the container): python3 make_svg.py <block.py> <out_basename>
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Runs the block (so its circuit is built, with __file__ set via runpy), then calls
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SKiDL generate_svg() on the resulting default circuit.
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"""
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import sys, runpy, os
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from skidl import generate_svg
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block, out = sys.argv[1], sys.argv[2]
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runpy.run_path(block, run_name="__main__") # builds default_circuit (also runs its ERC/netlist)
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generate_svg(file_=out) # netlistsvg -> <out>.svg
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print("SVG ->", out + ".svg")
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