367951c903
indicator.py: peak-detect (Schottky+RC) on STAGE1_OUT (signal-present) and MIX_OUT (clip) -> LM393 (powered from +15V) vs tunable threshold dividers -> open-collector outputs pulled to +3V3 = SIG_LED/CLIP_LED (drive face LEDs + read on GPIO19/20). speaker.py: PAM8302A filterless class-D (pinout verified, Diodes SO-8) fed from MIX_OUT (single-ended, RIN=68k -> ~+5.7dB), SD pulled high, BTL out -> SPK_P/SPK_N. Both ERC 0 errors; netlists 0 errors. Threshold/gain values tunable; DNP per form factor. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
51 lines
2.5 KiB
Python
51 lines
2.5 KiB
Python
#!/usr/bin/env python3
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"""PM_K-1 monitor speaker amp (SKiDL): PAM8302A class-D -> SPK_P/SPK_N. DNP/optional.
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Run INSIDE the EDA container:
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cd hardware/eda && ./run.sh python3 ../eda/circuits/speaker.py
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Outputs ERC + hardware/kicad/speaker.net.
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Filterless 2.5W mono class-D for a built-in monitor (populated only on form factors that
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want one). Fed from MIX_OUT (the mixed click+input, single-ended into IN+; IN- AC-coupled
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to GND). Gain = 20*log(150k/(10k+RIN)); RIN=68k -> ~+5.7dB. SD pulled high = enabled
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(route SPK_SD to a GPIO if software shutdown is wanted). Output is BTL (filterless) to the
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speaker via the analog interconnect.
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PAM8302A SO-8 pinout (Diodes, verified): 1=SD 2=NC 3=IN+ 4=IN- 5=VO+ 6=VDD 7=GND 8=VO-.
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"""
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import os
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from skidl import *
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set_default_tool(KICAD9)
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P = Pin.types
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R = Part("Device","R", dest=TEMPLATE, footprint="Resistor_SMD:R_0402_1005Metric")
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def C(v, fp="Capacitor_SMD:C_0402_1005Metric"): return Part("Device","C", value=v, footprint=fp)
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p5, p3v3, gnd = Net("+5V"), Net("+3V3"), Net("GND")
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for n in (p5, p3v3): n.drive = POWER
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gnd.drive = POWER
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mix_out, spk_p, spk_n, spk_sd = Net("MIX_OUT"), Net("SPK_P"), Net("SPK_N"), Net("SPK_SD")
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PAM = Part(name="PAM8302A", tool=SKIDL, dest=TEMPLATE, ref_prefix="U",
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footprint="Package_SO:SOIC-8_3.9x4.9mm_P1.27mm",
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pins=[Pin(num=1,name="SD",func=P.INPUT),Pin(num=2,name="NC",func=P.NOCONNECT),Pin(num=3,name="IN+",func=P.INPUT),
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Pin(num=4,name="IN-",func=P.INPUT),Pin(num=5,name="VO+",func=P.OUTPUT),Pin(num=6,name="VDD",func=P.PWRIN),
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Pin(num=7,name="GND",func=P.PWRIN),Pin(num=8,name="VO-",func=P.OUTPUT)])
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u = PAM(ref="U12")
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# supply
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u["VDD"] += p5; u["GND"] += gnd
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cb = C("1uF","Capacitor_SMD:C_0805_2012Metric"); p5 += cb[1]; cb[2] += gnd
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cd = C("100nF"); p5 += cd[1]; cd[2] += gnd
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# enable (SD high); route SPK_SD to a GPIO if desired
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rsd = R(value="100k"); spk_sd += rsd[1]; rsd[2] += p5; u["SD"] += spk_sd
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# single-ended input: MIX_OUT -> coupling cap + RIN -> IN+ ; IN- coupled to gnd (matched)
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cin = C("1uF","Capacitor_SMD:C_0805_2012Metric"); rin = R(value="68k") # ~+5.7dB
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mix_out += cin[1]; cin[2] += rin[1]; rin[2] += u["IN+"]
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cinm = C("1uF","Capacitor_SMD:C_0805_2012Metric"); u["IN-"] += cinm[1]; cinm[2] += gnd
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# filterless BTL output to speaker (via interconnect); add EMI ferrite/cap at layout if needed
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u["VO+"] += spk_p; u["VO-"] += spk_n
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ERC()
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out = os.path.abspath(os.path.join(os.path.dirname(__file__), "..", "..", "kicad", "speaker.net"))
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generate_netlist(file_=out)
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print("Speaker netlist ->", out)
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