DESIGN: route LCD TE pin on production face for tear-free updates

ST7796S datasheet §10.8: panel rescans GRAM at 60Hz; tear-free writes require feeding
the TE output back to the MCU and writing during vblank. EP-0172 prototype wires no TE,
so large updates tear (small writes hide it — why MP/CP look clean). Add TE (e.g. GP4)
+ optional MISO to the face interconnect for the production board.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>

hardware/DESIGN.md

@@ -172,6 +172,16 @@ Grounds interleaved around SPI. A Pico/Pico 2 test adapter maps these to the lis
 on-core — they are not on the ribbon. A Pico test brain drives the digital/face I/O above but
 **cannot** drive the analog chain (DAC/op-amps are core-only).*
 
+> **Display TE line — route it on the production face.** The table above mirrors the EP-0172
+> prototype, which wires only SCK/MOSI/CS/DC/RST and **no TE (tearing-effect) output**. Per the
+> ST7796S datasheet §10.8, the panel rescans its frame memory to the glass at 60 Hz and the *only*
+> sanctioned way to avoid tearing is to feed the **TE output back to the MCU** and write during
+> vblank (`tvdh`). Without it, large updates tear and only small sub-region writes hide it (this is
+> why MicroPython/CircuitPython, which draw glyph-by-glyph, look clean and the Rust full-frame blits
+> don't). **Add the LCD `TE` pin to a spare GPIO (e.g. GP4)** on the face interconnect — and
+> optionally LCD `MISO`/`SDO` for `GSCAN`(45h)/status reads. Then firmware can do
+> `TEON`(35h)+vblank-synced writes and be fully tear-free even on full repaints.
+
 ### 7.2 Analog audio interconnect — 2×5 (10-pin), twisted/shielded, away from digital
 | Pin | Signal | | Pin | Signal |
 |----|--------|--|----|--------|