PM_K-1 hardware: Stage 3 -- summing node (selected input + click)
Inverting summing amp (OPA1612 section) mixes STAGE1_OUT (line/instrument) and CLICK_OUT (filtered DAC) at unity into MIX_OUT. Each source enters its own 10k into the op-amp virtual ground, so they sum with no interaction. stage3_sum.cir confirms: each input alone = 0 dB, both together = +6.02 dB, and each input's gain is unchanged by the other (virtual-ground isolation). ERC/netlist 0 errors. Note: inverting summer flips phase -> corrected at the Stage 4 balanced driver via hot/cold assignment. At integration, this summer can use the parked 2nd half of the Stage 2 filter OPA1612 (U4) instead of a separate package. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
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69
hardware/eda/circuits/stage3_sum.py
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hardware/eda/circuits/stage3_sum.py
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#!/usr/bin/env python3
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"""PM_K-1 audio chain - Stage 3: summing node (selected input + click) (SKiDL).
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Run INSIDE the EDA container:
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cd hardware/eda && ./run.sh python3 ../eda/circuits/stage3_sum.py
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Outputs ERC + a KiCad netlist at hardware/kicad/stage3_sum.net.
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WHAT THIS STAGE DOES
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Inverting summing amp (OPA1612 section) mixes STAGE1_OUT (the line/instrument input,
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unity) and CLICK_OUT (the filtered DAC click). Each source enters through its own
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10k resistor into the op-amp's virtual-ground node, so the two never interact. The
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"digital mix" lives upstream: click level is set by the DAC; the input passes at
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unity. Output MIX_OUT -> Stage 4 balanced driver.
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Vout = -(STAGE1_OUT + CLICK_OUT) (Rf = Ri = 10k)
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POLARITY: an inverting summer flips phase. That is corrected for free at the Stage 4
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balanced driver by assigning hot/cold accordingly (absolute polarity preserved).
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OPA1612 dual: standard JEDEC pinout (1=OUTA 2=-INA 3=+INA 4=V- 5=+INB 6=-INB 7=OUTB
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8=V+). At INTEGRATION this summer can use the PARKED 2nd half of the Stage 2 filter's
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OPA1612 (U4) instead of a separate package -- noted for the merge step.
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"""
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import os
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from skidl import *
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set_default_tool(KICAD9)
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R = Part("Device", "R", dest=TEMPLATE, footprint="Resistor_SMD:R_0805_2012Metric")
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C = Part("Device", "C", dest=TEMPLATE, footprint="Capacitor_SMD:C_0805_2012Metric")
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p15, n15, gnd = Net("+15V"), Net("-15V"), Net("GND")
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for n in (p15, n15, gnd):
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n.drive = POWER
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stage1_out = Net("STAGE1_OUT") # from Stage 1b relay (selected input)
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click_out = Net("CLICK_OUT") # from Stage 2 reconstruction filter
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mix_out = Net("MIX_OUT") # -> Stage 4 balanced driver
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OPA2 = Part(name="OPA1612", tool=SKIDL, dest=TEMPLATE, ref_prefix="U",
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footprint="Package_SO:SOIC-8_3.9x4.9mm_P1.27mm",
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pins=[
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Pin(num=1, name="OUTA", func=Pin.types.OUTPUT),
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Pin(num=2, name="-INA", func=Pin.types.INPUT),
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Pin(num=3, name="+INA", func=Pin.types.INPUT),
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Pin(num=4, name="V-", func=Pin.types.PWRIN),
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Pin(num=5, name="+INB", func=Pin.types.INPUT),
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Pin(num=6, name="-INB", func=Pin.types.INPUT),
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Pin(num=7, name="OUTB", func=Pin.types.OUTPUT),
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Pin(num=8, name="V+", func=Pin.types.PWRIN),
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])
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u = OPA2(ref="U5")
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# inverting summer: each source -> 10k -> virtual-ground (-INA); Rf 10k; +INA -> gnd
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ri_in, ri_clk, rf = R(value="10k"), R(value="10k"), R(value="10k")
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stage1_out += ri_in[1]; ri_in[2] += u["-INA"]
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click_out += ri_clk[1]; ri_clk[2] += u["-INA"]
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rf[1] += u["-INA"]; rf[2] += u["OUTA"]
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u["+INA"] += gnd
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u["OUTA"] += mix_out
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# supplies + decoupling; park unused section B
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u["V+"] += p15; u["V-"] += n15
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for rail in (p15, n15):
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c = C(value="100nF"); rail += c[1]; c[2] += gnd
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u["+INB"] += gnd; u["OUTB"] += u["-INB"] # parked follower
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ERC()
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out = os.path.abspath(os.path.join(os.path.dirname(__file__), "..", "..", "kicad", "stage3_sum.net"))
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generate_netlist(file_=out)
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print("Stage 3 netlist ->", out)
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40
hardware/eda/sim/stage3_sum.cir
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hardware/eda/sim/stage3_sum.cir
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* PM_K-1 Stage 3 : summing node (selected input + click)
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*
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* An inverting summing amp mixes STAGE1_OUT (line/instrument) and CLICK_OUT (DAC).
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* Each source feeds the op-amp's inverting input through its own 10k resistor; the
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* feedback holds that node at a "virtual ground" (~0V). Because BOTH sources see 0V
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* there, neither can load or pull on the other -- they sum with no interaction.
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* Vout = -(Rf/Ri1)*V1 - (Rf/Ri2)*V2 ; with Rf=Ri=10k -> Vout = -(V1+V2).
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*
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* We confirm: each input alone = 0 dB (gain -1), both together = +6 dB (they add),
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* and each input's gain is unchanged by the other (isolation).
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* Run: ngspice -b ../eda/sim/stage3_sum.cir
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.title Stage3 inverting summer
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Vinp inp 0 AC 1 ; selected input (STAGE1_OUT)
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Vclk clk 0 AC 1 ; filtered click (CLICK_OUT)
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Ri1 inp vm 10k
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Ri2 clk vm 10k
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Rf vm out 10k
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Eop out 0 0 vm 1e6 ; +in = gnd, -in = vm -> inverting; feedback makes vm a virtual ground
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.ac dec 10 100 20k
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.control
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* both sources active -> they sum
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run
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meas ac g_both find vdb(out) at=1k
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echo " both = $&g_both dB (+6 dB over each-alone = the two sum)"
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* input alone (click muted)
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alter @Vclk[acmag]=0
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run
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meas ac g_in find vdb(out) at=1k
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echo " input alone = $&g_in dB (gain -1, i.e. 0 dB)"
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* click alone (input muted)
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alter @Vinp[acmag]=0
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alter @Vclk[acmag]=1
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run
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meas ac g_clk find vdb(out) at=1k
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echo " click alone = $&g_clk dB (gain -1; unchanged by the input = virtual-ground isolation)"
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.endc
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.end
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5
hardware/kicad/stage3_sum.erc
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hardware/kicad/stage3_sum.erc
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ERC WARNING: Only one pin (PASSIVE pin 1/~ of R/R1) attached to net STAGE1_OUT.
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ERC WARNING: Only one pin (PASSIVE pin 1/~ of R/R2) attached to net CLICK_OUT.
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ERC INFO: 2 warnings found while running ERC.
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ERC INFO: 0 errors found while running ERC.
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hardware/kicad/stage3_sum.log
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hardware/kicad/stage3_sum.log
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WARNING: KICAD8_SYMBOL_DIR environment variable is missing, so the default KiCad symbol libraries won't be searched. @ [/work/hardware/kicad/<frozen importlib._bootstrap_external>:995=>/work/hardware/kicad/<frozen importlib._bootstrap>:488]
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WARNING: KICAD6_SYMBOL_DIR environment variable is missing, so the default KiCad symbol libraries won't be searched. @ [/work/hardware/kicad/<frozen importlib._bootstrap_external>:995=>/work/hardware/kicad/<frozen importlib._bootstrap>:488]
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WARNING: KICAD7_SYMBOL_DIR environment variable is missing, so the default KiCad symbol libraries won't be searched. @ [/work/hardware/kicad/<frozen importlib._bootstrap_external>:995=>/work/hardware/kicad/<frozen importlib._bootstrap>:488]
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WARNING: fp-lib-table file was not found. Component footprints are not available.
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WARNING: fp-lib-table file was not found. Component footprints are not available.
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WARNING: fp-lib-table file was not found. Component footprints are not available.
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WARNING: fp-lib-table file was not found. Component footprints are not available.
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WARNING: Missing tag on OPA1612 instantiated at /work/hardware/eda/circuits/stage3_sum.py:50.
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WARNING: Random tag 5n2wh6xRRe generated for OPA1612.
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WARNING: Missing tag on R instantiated at /work/hardware/eda/circuits/stage3_sum.py:53.
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WARNING: Random tag PsTgUzSm6S generated for R.
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WARNING: Missing tag on R instantiated at /work/hardware/eda/circuits/stage3_sum.py:53.
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WARNING: Random tag MJ5MDnj_yt generated for R.
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WARNING: Missing tag on R instantiated at /work/hardware/eda/circuits/stage3_sum.py:53.
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WARNING: Random tag RyhIEBAL2O generated for R.
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WARNING: Missing tag on C instantiated at /work/hardware/eda/circuits/stage3_sum.py:63.
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WARNING: Random tag oOB0ftP80i generated for C.
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WARNING: Missing tag on C instantiated at /work/hardware/eda/circuits/stage3_sum.py:63.
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WARNING: Random tag NmK6U68Pr1 generated for C.
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WARNING: Missing tag on instantiated at /work/hardware/kicad/<frozen importlib._bootstrap>:488.
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INFO: 17 warnings found while generating netlist.
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INFO: 0 errors found while generating netlist.
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hardware/kicad/stage3_sum_sklib.py
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hardware/kicad/stage3_sum_sklib.py
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from collections import defaultdict
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from skidl import Pin, Part, Alias, SchLib, SKIDL, TEMPLATE
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from skidl.pin import pin_types
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SKIDL_lib_version = '0.0.1'
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stage3_sum = SchLib(tool=SKIDL).add_parts(*[
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Part(**{ 'name':'OPA1612', 'dest':TEMPLATE, 'tool':SKIDL, 'aliases':Alias({'OPA1612'}), 'ref_prefix':'U', 'fplist':None, 'footprint':'Package_SO:SOIC-8_3.9x4.9mm_P1.27mm', 'keywords':None, 'description':'', 'datasheet':None, 'pins':[
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Pin(num='1',name='OUTA',func=pin_types.OUTPUT),
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Pin(num='2',name='-INA',func=pin_types.INPUT),
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Pin(num='3',name='+INA',func=pin_types.INPUT),
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Pin(num='4',name='V-',func=pin_types.PWRIN),
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Pin(num='5',name='+INB',func=pin_types.INPUT),
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Pin(num='6',name='-INB',func=pin_types.INPUT),
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Pin(num='7',name='OUTB',func=pin_types.OUTPUT),
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Pin(num='8',name='V+',func=pin_types.PWRIN)] }),
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Part(**{ 'name':'R', 'dest':TEMPLATE, 'tool':SKIDL, 'aliases':Alias({'R'}), 'ref_prefix':'R', 'fplist':[''], 'footprint':'Resistor_SMD:R_0805_2012Metric', 'keywords':'R res resistor', 'description':'Resistor', 'datasheet':'~', 'pins':[
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Pin(num='1',name='~',func=pin_types.PASSIVE,unit=1),
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Pin(num='2',name='~',func=pin_types.PASSIVE,unit=1)], 'unit_defs':[] }),
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Part(**{ 'name':'C', 'dest':TEMPLATE, 'tool':SKIDL, 'aliases':Alias({'C'}), 'ref_prefix':'C', 'fplist':[''], 'footprint':'Capacitor_SMD:C_0805_2012Metric', 'keywords':'cap capacitor', 'description':'Unpolarized capacitor', 'datasheet':'~', 'pins':[
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Pin(num='1',name='~',func=pin_types.PASSIVE,unit=1),
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Pin(num='2',name='~',func=pin_types.PASSIVE,unit=1)], 'unit_defs':[] })])
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