# Schematic views (auto-generated)

Per-block schematic images of the PM_K-1 core board, rendered from the SKiDL circuits with
**netlistsvg**. Open any `.svg` in a web browser.

**What these are:** functional, auto-routed schematics (boxes + wires) for *tracing
connections* — not hand-arranged, pretty EE drawings. Each file is one block, so it's
readable; the full 167-part board would be an unreadable hairball.

| File | Block |
|---|---|
| `stage1_input.svg` | balanced line receiver + protection |
| `stage1b_select.svg` | Hi-Z instrument DI buffer + select relay |
| `stage2_dac.svg` | PCM5102A DAC + reconstruction filter |
| `stage3_sum.svg` | summing node |
| `stage4_driver.svg` | balanced output driver + mute + ground-lift |
| `audio_chain.svg` | the five audio stages integrated (busier) |
| `power_tree.svg` | ±18 V switcher → ±15 V LDOs + 3V3 |
| `mcu_core.svg` | RP2350 + flash + crystal + USB + boot/SWD |
| `rtc.svg` | RV-8803 RTC + coin-cell backup |
| `midi.svg` | DNP opto IN + buffered OUT/THRU |
| `indicator.svg` | SIG/CLIP detector |
| `speaker.svg` | monitor speaker amp |

**`interconnect` is intentionally absent** — netlistsvg's layout engine errors on the
24-pin USB-C + many headers. Its connections are pure pin-to-net mapping, fully tabulated
in `hardware/DESIGN.md` §7 and `circuits/interconnect.py`.

**Regenerate** (inside the container): for each block,
`./run.sh python3 ../eda/make_svg.py circuits/<block>.py schematics/<block>` then
`netlistsvg schematics/<block>.json -o schematics/<block>.svg --skin schematics/<block>_skin.svg`.

For the authoritative, hand-written design intent see the `circuits/*.py` files and
`hardware/DESIGN.md` block diagrams; for the connection list see `hardware/kicad/board.net`.
